Classifying DTLB miss addresses from User and Kernel

Classifying DTLB miss addresses from User and Kernel

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 I was wondering if Intel PTU can help distinguish between DTLB misses that fall on kernel memory and those that fall on user memory. Please note that this is different from classifying DTLB misses occurring in kernel mode and those in user mode since acces user land memory can occur in kernel mode( e.g., system calls accessing user memory). I think this might be possible using PEBS (precise-event-based-sampling) hardware feature and by regenerating linear address of sampled DTLB miss event (linear address of kernel memory and user land memory would be in very different range and thus distinguishable).   However, my question is whether Intel PTU can already do this.





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