TITLE: Back End Bound Due To Latency Caused By L2 Cache
Cycles the back end was bound on the L2 cache
This metric represents how often the pipeline was back end bound on the L2 cache. Avoiding cache misses (i.e. L1 misses/L2 hits) will improve the latency and increase performance.
For instance, if you have many L1 misses and hit in the L2 cache, you would see a high percentage of back end memory bound percentage in L2.
EQUATION: (CYCLE_ACTIVITY.STALLS_L1D_PENDING-CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD