intel phi bandwith

intel phi bandwith

Hi All,

      I am writing an application on MIC architecture,  I want to know the bandwith between each memory device.

Like bandwidth between core and L1, L1 and L2, L2 and memory.  I want these information to evaluate my application.

So I want to know how many Load can be issued each clock cycle. ? 

How many cycles needed to translate a 64byte cache line from L2 to L1 ?

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I am a little urgent  for these data, please help me. Thank you~

I think that VTune for Linux can be helpful in your case.You can also try to ask your question on MIC forum.

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