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Intel® Xeon Phi™ Coprozessor

Produktivität durch innovative Architektur plus bewährte Software. Intel® Xeon Phi™ Coprozessor:

  • Bietet Hardware-Unterstützung für mehr Parallelität und stromsparenderes Verhalten
  • Verwendet bewährte Standard-Programmiermodelle, damit sich bisherige Investitionen weiter lohnen
  • Geteiltes Parallel Programming mit Allzweckprozessor

Neu! Anwendungskatalog

Durchstöbern Sie die wachsende Liste mit verfügbarem, herunterladbarem oder in Entwicklung befindlichem Code, der auf Intel® Xeon Phi™ Coprozessoren ausgeführt werden kann oder aktiv für die Ausführung darauf optimiert ist.

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Erste Schritte
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Bezugsquellen
Intel® Xeon Phi™ Coprozessor Architektur
Sitemaps: Administratoren, Entwickler, Forscher
Anleitungen und Handbücher
Intel® Xeon Phi™ Coprozessor - Schnellanleitungen für Entwickler
Intel® Xeon Phi™ Coprozessor - Referenzhandbuch zur Befehlssatzarchitektur
Systemadministrationshandbuch

Parallel Programming gehört zu den zukunftsträchtigsten Modellen. Intel Prozessoren und Coprozessoren bieten eine kombinierte Methode, damit Sie gängige Programmiermodelle und -tools verwenden können.

  • Standardgestützte Parallel Programming Modelle mit Skalierbarkeit für heute und die Zukunft
  • Verwenden bewährte Entwicklungs-Workflows und Codebasis für vorwärts gerichtete Skalierung
  • Methoden nutzen sowohl Prozessoren als auch Coprozessoren, damit sich vergangene und zukünftige Investitionen langfristig lohnen
Programmierung für Multicore- und Manycore-Produkte
Code-Rezepte für den Intel® Xeon Phi™ Coprozessor

Programmierung

Intel® Xeon Phi™ Coprozessor - Anleitung für Softwareentwickler

Entwicklung nativer Anwendungen

Programmierung und Kompilierung

Spickzettel: Direktiven und Funktionen

Automatisches Offload für Math Kernel Library

Verwendung von Intel® MPI

Verwendung der OpenMP* Extensions

OpenCL* Design und Programmierung

System V Application Binary Interface

Unterschiede bei der Gleitkomma-Arithmetik

Reproduzierbarkeit zwischen Läufen

Leistungsanalyse und -konfiguration

Migration von Fortran Projekten

Debugging

Debugging auf Linux*

Debugging auf Windows*

Optimierung

Optimierung – Teil 1: Grundlagen

Optimierung – Teil 2: Hardware-Ereignisse

Leistungsüberwachungs-Einheiten

Loop-Optimierung

Bewährte Methoden für Leistung

      Neueste Beiträge

      Intel Xeon Phi Coprocessor April 2013 Developer Webinar Q&A Responses
      Von robert-reed (Intel)Veröffentlicht am 05/10/20130
      Answers for the questions raised during the April session of our Introduction to High Performance Application Development for Intel® Xeon® & Intel® Xeon Phi™ processors class have been assembled.  There were some duplicates and other questions we couldn't decipher, either because of the wording…
      Windows* early enabling for Intel® Xeon Phi™ Coprocessors
      Von BELINDA L. (Intel)Veröffentlicht am 05/08/20134
      *** UPDATE September 2013 - PLEASE READ *** This Beta program is officially closed, as a production version of the software drivers, and supporting Intel(R) compilers are now available.   Here is where to get each: Software Drivers:  http://software.intel.com/en-us/articles/intel-manycore-platform-…
      Intel® SDK for OpenCL* Applications XE 2013 Release Notes
      Von Jeffrey Mott (Intel)Veröffentlicht am 05/08/20130
      Intel® SDK for OpenCL* Applications XE 2013 Release Notes Content Introduction What's New System Requirements Installation Notes Issues and Limitations Legal Information Introduction The Intel® SDK for OpenCL* Applications XE 2013 is a software development environment for OpenCL* applicat…
      A case study comparing AoS (Arrays of Structures) and SoA (Structures of Arrays) data layouts for a compute-intensive loop run on Intel® Xeon® processors and Intel® Xeon Phi™ product family coprocessors
      Von pjbesl (Intel)Veröffentlicht am 05/06/20130
      by Paul Besl Download full case study in PDF format Download Download accompanying source code (ZIP format) Download Abstract A customer recently purchased a significant number of Intel Xeon Phi coprocessors to augment the capabilities of their cluster of 16-core dual-socket compute nodes based on…
      Intel Developer Zone Beiträge abonnieren
      Viable configuration for a home lab - 8 31S1P on 4 slot pcie 3.0 motherboard?
      Von Robert F.5
       Building my basement laboratory for math, machine learning, parallel programming, kagglng... Is it electrically possible to mount 2 cards per PCIE 3.0 x16 slot with daughter boards and extenders on a motherboard. At 300 watts per card tdp  it would likely take - 3 1000 watt power supplies BUT can we get enough power to the individual MIC's in this kind of configuration? Being able to spend on compute cards rather than infiniband switches/cards and platforms seems like a better way to spend the allowance my wife lets me keep if possible.   Thanks, Robert      
      Intel MPSS on Ubuntu and Mellanox OFED 2.3
      Von Patrice H.3
      Hi, We recently installed a PHI on a Dell R720 server running Ubuntu 14.04 with Mellanox OFED 2.3 From https://software.intel.com/en-us/blogs/2014/09/23/working-with-mellanox-... at section 2.3, there is instructions to install Mellanox OFED 2.1 to support host IB adapter. I am running Mellanox OFED 2.3.1 and can't take it down to 2.1. The question is: Is it possible to work with Mellanox OFED 2.3.1 on the PHI? If I follow the instruction in the above mentionned documentation, I will end up in downgrading the Mellanox DAPL package from dapl 2.1.1 to dapl 2.0.42, and I don't expect it to work. Thanks!
      phi access
      Von Claus D.3
      Hi all, I am currently preparing an introductory course for HPC for some phd students at our university. We will work on some very simple example codes (openmp and mpi) and test them on small clusters we have here. Is there any possibility to have access to a phi so I could try to run some of this code on it to see how it behaves/scales?  Kind regards!
      streaming video thru Phi
      Von Andres G.1
      I am currently developing a real-time video processing application that runs on a dedicated 2-CPU Xeon linux box.  The application supports multiple video inputs and multiple video outputs with standard image processing like picture-in-a-picture, graphics and language-specific text overlay, etc. It is basically a pipeline-based architecture where a given input video stream is over laid with language-specific text overlays, then each language specific stream is output on a separate output. I currently know nothing about Phi or GPU programming; only that it is for applications that can be structured for parallel processing like vector processing for example.  I do not know if it is a good choice for my particular application so I thought I would ask a high level newbie question. Q: Is the memory transfer bandwidth between host Xeon CPU memory to the Phi memory sufficient to support multiple video streams?  The Phi seems appropriate for image processing once the image is in the Phi memor…
      Regarding util_mic_set_affinity_ error while compiling NWChem with icc
      Von puneet s.4
      I am trying to compile Intel(R) Xeon(R)  E5-2670 v2 to verify the benchmarks , published here .I first want to verify the performance benchmark on my host processor , though later i will compile it for the Intel MIC. Presently i am am stuck at an error (attached: make_logs_unseting4.txt) regarding mic routines even though i have not enabled any offload flag( unset USE_OFFLOAD after sourcing nwchem_make_env.sh.txt ).  Variables on my path:(attached: nwchem_make_env.sh.txt) Please help me regarding finding out the root cause of this problem. Eagerly awaiting your reply, Regards, Puneet
      Using the Phi in the class room in a multi-user environment
      Von Alan P.2
      Howdy, We just acquired systems with Phi cards for Academic use. Our first programming class using the cards is about to start, and we are new to the both the development flow and to what we need to do for multi-user academic use. For instance we are not able to use our Active Directory accounts on the Phi card (even though they work on the CentOS host system). Could folks here point me to resources related to: class-room use,  multi-user environments with remote authentication, and possible cautions related to student users? Thanks in advance,   -Alan  
      Intel Phi compiling cl file occurs Stack dump: Segmentation fault (core dumped) Y86 DAG->DAG and Function Pass Manager
      Von Roysky l.1
      hi,everyone when i compile the cl file on Intel Many Integrated Core and linux system,i gets the below errors Stack dump: 0.      Running pass 'Function Pass Manager' on module 'Program'. 1.      Running pass 'Y86 DAG->DAG Instruction Selection' on function '@test_kernel' Segmentation fault (core dumped) who can get me some suggestions? Thank you! here is my code of OpenCL kernel __kernel void test_kernel(__global Byte64 *dicPwd) {  unsigned int tid = get_global_id(0),tidloop=0;  unsigned int  g_TotalThread = get_global_size(0);  int pwdlen=0;    Byte64 data=dicPwd[tid];  unsigned char *pUniPwd = data.c;  pwdlen=data.c[63];  unsigned char keyCopy[8];  for (unsigned int i = 0; i < 8; i++)   keyCopy[i] = i;  for (unsigned int i = 0; i < pwdlen; i++)  {   unsigned char tmp0 =keyCopy[i % 7];   unsigned char tmp1 = tmp0 ^pUniPwd[i];   unsigned char tmp2 = (unsigned char)(tmp1 >> 1);   unsigned char tmp3 =(unsigned char) (tmp1 << 7);   keyCopy[i % 7] = (unsigned c…
      Online SAP HR training in Hyderabad USA,UK,Canada,Australia,India,Dubai, @ +91 800 8000 311
      Von letslearn g.0
      SAP HR COURSE   INTRODUCTION   • What is SAP? • ASAP Methodology • About versions and Architecture • SAP landscape • HR in SAP • Why SAP HR as ERP Solution for a company   STRUCTURES IN SAP HR/HCM   • Enterprise Structure • Personnel Structure • Organizational Structure   ORGANIZATIONAL MANAGEMENT   • Overview of Organizational Objects and Structures • Creating and interpreting positions • Relationships • Infotype Maintenance • Simple Maintenance • Expert Mode • Reporting Structure • Maintenance of Plan versions • Maintenance of Number Ranges for Objects   PERSONNEL ADMINISTRATION   • Personnel Area, Personnel Sub Area, Employee Group, Employee Sub Group                          Assignment of ES & PS                          Personnel Action, Hiring   • Maintaining Master Data • Maintaining Infotypes • Orientation of Features and Configuration • Creation of Infogroups • Configuration of Personnel Actions • Maintaining Infotype Menus • Defaulting the User Parameters • Dynamic…
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