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Hier finden Sie Informationen zu Leistungsüberwachung und Software-Tuning sowie Themen zur Plattformüberwachung. Die Leistungsüberwachung deckt eine Reihe von Themen ab, darunter eine Einführung zu Überwachungs- und Software-Tuning-Methodiken sowie Strategien zur Softwareoptimierung und bewährte Methoden für Anfänger und fortgeschrittene Benutzer.

Für Entwickler stehen Programmierreferenzhandbücher zur Verfügung, die alle Neuheiten zur Hardwareschnittstelle der Performance Monitoring Unit (PMU) bei den Intel Mikroprozessoren beschreiben, darunter Kern- und Nicht-Kern-Überwachungsressourcen sowie die definitive Informationsquelle zu Leistungsereignissen, die überwacht werden können.

Zu der Plattformüberwachung gehören Themen zur Geräteüberwachung wie die Überwachung von CPU-Kern, Grafikprozessoren und anderen System-Coprozessoren sowie zur Messung des Quality of Service.

Merrifield Uncore Performance Monitoring Events
Von SAI SINDURI G. (Intel)Veröffentlicht am 05/20/20140
Using the Merrifield SoC Performance Monitoring Events This article focuses directly on the uncore performance monitoring events for the SoC Merrifield.  For the introduction to SoC uncore performance monitoring, please see this article: Silvermont SoC Uncore Performance Monitoring Guide Introduc…
Rangeley Uncore Performance Monitoring Events
Von Perry Taylor (Intel)Veröffentlicht am 05/09/20140
Using the Rangeley SoC Performance Monitoring Events This article focuses directly on the uncore performance monitoring events for the SoC Rangeley.  For the introduction to SoC uncore performance monitoring, please see this article: Silvermont SoC Uncore Performance Monitoring Guide Introduction…
Baytrail Uncore Performance Monitoring Events
Von Perry Taylor (Intel)Veröffentlicht am 04/16/20140
Using the Baytrail SoC Performance Monitoring Events This article focuses directly on the uncore performance monitoring events for the SoC Baytrail.  For the introduction to SoC uncore performance monitoring, please see this artictle: Silvermont SoC Uncore Performance Monitoring Guide Introductio…
Silvermont SoC Uncore Performance Monitoring Guide
Von Perry Taylor (Intel)Veröffentlicht am 04/10/20140
Welcome to the System on a Chip (SoC) uncore performance monitoring guide.  This article will introduce you to the SoC uncore performance monitoring event set and provide details on the events and how to interpret results. The Silvermont generation of SoCs features a new set of uncore performanc…
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Scope of MXCSR control register?
Von tran l.0
scope of MXCSR control register is scope of thread, is it? That it mean: Default FTZ is OFF. Thread A set FTZ to ON. After that, in all others threads, FTZ is still OFF. I refer to link: http://stackoverflow.com/questions/4948057/scope-of-mxcsr-control-register  
microcode processor update: what processors are supported and what version is inside update?
Von Peter V.0
Hi! I've asked this question at community forums https://communities.intel.com/message/312574 and I was suggested to ask here.    Intel provides Processor microcode update. Is it possible to find out what CPUs are supported and what microcode version is inside update? For example, what CPUs this update: Intel® Download Center supports and what microcode version is expected to appear after upgrade?   The reason I'm asking is the following: we have a trouble with some HP and Supermicro servers: after some time kernel errors out with MCE error (Machine Check Exception: 4 Bank 5: be00000000800400). It is possible to find many bug reports, e.g. https://bugzilla.redhat.com/show_bug.cgi?id=715485, and suggested fix was to upgrade bios. Bios upgrade was expected to fix many processor issues (Drivers & Software - HP Support Center) and it updated microcode version from 0x14 to 0x1a.Yet we still experience this problem on some servers after bios upgrade. It looks like qemu running on this s…
Performance seems not stable after using AES-NI for data encryption/decryption
Von Xuehan X.0
Hi, everyone. I've got a need to encrypt data written from a virtual machine on XenServer. I added a pure software AES CBC encryption method to the Xen virtual disk read/write operation, and test the write throughput by runing the following command in the VM: dd if=/dev/zero of=/mnt/test_file bs=512 count=1048576and the tested throughput is about: 55 MB/s. I modified the encryption method to use the Intel AES-NI for encryption/decrytion, and run the former test several times, and the result is as follows: Test 1: 85.1 MB/s Test 2: 72.0 MB/s Test 3: 56.0 MB/s Test 4: 95.9 MB/s Test 5: 43.5 MB/s Test 6: 61.5 MB/s Test 7: 74.5 MB/s Test 8: 43.3 MB/s Test 9: 63.8 MB/s Test 10: 94.8 MB/s Test 11: 110 MB/s Although the average throughput is about 40% higher than that using the pure software method, the throughput seems to be very unstable. Why? Is there anyway to stablize it? Thank you:-)  
How hardware prefetcher change load and store buffer behavior in processor pipeline
Von Zhu G.3
Hi, Community! I am experimenting with XEON E5620 dual socket server. I perf with event RESOURCE_STALLS.LOAD and RESOURCE_STALLS.STORE in SDM page 2699 of chapter 19.7. I first turned off hardware prefetch following instructions on url: https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-co... the instruction I used is : wrmsr -a 0x1a4 0xf then I used perf command as: perf stat -e ra202,ra208 ./fft-m26 the result is : 201 ra202 10,215,615 ra208 29.485852761 seconds time elapsed then I enabled hardware prefetch using : wrmsr -a 0x1a4 0x0 again I perf with: perf stat -e ra202,ra208 ./fft-m26 As I wished I get better performance, the result is : 2,206 ra202 18,970,999 ra208 24.963877684 seconds time elapsed But I observed that it seems the pipeline has stalled more on load buffer and store buffer. Why is this?
Counting native events
Von Vincent B.2
Hi, I try to count some performance events of a part of an application written in C. So far, I have used PAPI to count events. It works fine for preset events. However, when I profile native events, all of them turn out to be translated into the same Event Code : 0x40000022 (an output of papi_avail is below). It makes no sense, but no error occurs when I profile them. What could be wrong ? How could I debug this ? Also, I've got a list (from the perfmon directory) of events that can be counted for the architecture I work with (Ivy bridge) and the adresses and values of the associated registers. Is there an alternative to PAPI I could use to count a particular event of that list, over a certain part of the program, knowing the name of the event and the registers informations ? Would it work to simply write and read to the corresponding registers manually (for example using pcm-msr) ? Thanks in advance for your help, Vincent   $ papi_avail -e LLC_MISSES Available events and hardware inf…
How vtune compute bandwith?
Von HUIZHAN Y.1
Hi, I am analyzing a simulated cannealling program from parsec. The program often access elem data randomly, so it have poor performance. I add a prefetching instruction for elem, and I am glad to see the time of parallel region with multiple threads has been reduced from 31 second to 15 second. Indeed it is a good result. I just prefetch the data in advance one iteration, and I wish get more performance improvement. But after adjusting the prefetching parameter, I cannot get much better result. So I doubt the prefetching has used up all bandwidth when prefetching the data in advance one iteration. So I check the bandwidth with vtune bandwidth analysis after the prefetching, and I found that the bandwidth only was increased a few from 3.004GB/s to 3.268 (for a single package). I feel the result is not right. Since adding prefetching do not add loaded data size, the time is reduced to a half from 31s to 15s, the bandwidth should be equal to  DATA_SIZE/TIME, so the bandwidth should be d…
Package C-State PC6/PC7 on Linux
Von Michael M.0
Hi, I have an i5 4590T processor, I'm running Ubuntu Linux. The package c-state never goes above pc3. I've searched all over for a solution, and tried all of the suggestions I've found, but none of them work. I've set all of the Tunables in PowerTOP to good. I've enabled ASPM. It's enabled on all of the PCI devices: lspci -vvvv | grep ASPM LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+ LnkCap: Port #5, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <16us LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+ LnkCap: Port #0, Speed 2.5G…
Error reading llc_misses event in Xeon D-1540
Von Roberto R.4
Hello everyone,  I am working in a tool that permits to access the different hardware events through performance counters (PMC). This tools works great I have tested in several Intel processors, SandyBridge, Haswell and Haswel-EP. Now I am working with a Broadwell processor that has some new cache monitoring features I need to work with.  Trying my tool in this processor I found that the events, described in 64-ia-32-architectures-software-developer-manual-325462.pdf Table 19.1, LLC Reference (2EH, Umask 4FH) and LLC Misses (2EH, Umask 41H) report the same number.  I though this could be an error from my tool so I tried perf and I got the same error. Also I can use only 4 programable PMCs, it is supposed to have 8 programmable PMCs, if I tried to use a 5th PMC it returns zero, same happend with perf. My processor is: Intel(R) Xeon(R) CPU D-1540 @ 2.00GHz Vendor    : GenuineIntel Family    : 6 Model    : 6 Stepping: 2 Type    : OEM The perf output is: $ perf stat -I 1000 -e instr…
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Am 5. Januar 2011 hat Intel die Intel® Core™ Prozessoren der 2. Generation (zuvor unter dem Codenamen Sandy Bridge bekannt) für Notebooks und PCs vorgestellt. Die neuen Prozessoren besitzen eine revolutionäre neue Architektur, die zum allerersten Mal das "Rechengehirn" (den Mikroprozessor) mit einem Grafikmodul auf demselben Chip kombiniert. Neue Features umfassen Intel® Insider™, Intel® Quick-Sync-Video und eine neue Version des preisgekrönten Intel® Wireless-Display (WiDi), welches nun Full-HD und einen Schutzmechanismus unterstützt, für Benutzer die Premium-HD-Inhalte von ihren Notebook auf ihren Fernsehbildschirm übertragen möchten.

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