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The Chronicles of Phi - part 5 - Plesiochronous phasing barrier – tiled_HT3

For the next optimization, I knew what I wanted to do; I just didn’t know what to call it. In looking for words that describes loosely-synchronous, I came across plesiochronous:

Autor: jimdempseyatthecove Zuletzt aktualisiert am 29.07.2015 - 00:02
Article

Diagnostic 15542: Loop was not vectorized: inner loop was already vectorized.

Product Version: Intel(R) Visual Fortran Compiler XE 15.0 or a later version

Autor: Devorah H. (Intel) Zuletzt aktualisiert am 23.07.2015 - 14:06
Blog post

Unity Configuration Tips: Memory, Audio, and Textures

Tips and Tricks on memory optimization and working with textures and was compiled by Steve Hughes who works as an Applications Engineer for Visual Computing at Intel. Tips include textures, design tips, mesh modeling, audio, and memory optimization.
Autor: Colleen Culbertson (Intel) Zuletzt aktualisiert am 22.07.2015 - 12:08
Blog post

Intel® RealSense™ Navigation Library Sample Code

The Intel® RealSense™ Navigation Library is a code sample that demonstrates how to easily add no-touch navigation to a web application. Colleen Culbertson describes its content and tells you where to get it.
Autor: Colleen Culbertson (Intel) Zuletzt aktualisiert am 22.07.2015 - 10:16
Blog post

The Chronicles of Phi - part 4 - Hyper-Thread Phalanx – tiled_HT2

The prior part (3) of this blog showed the effects of the first-level implementation of the Hyper-Thread Phalanx.

Autor: jimdempseyatthecove Zuletzt aktualisiert am 21.07.2015 - 17:57
Blog post

The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and…
Autor: jimdempseyatthecove Zuletzt aktualisiert am 21.07.2015 - 17:57
Blog post

The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued

The prior part (2) of this blog provided a header and set of function that

Autor: jimdempseyatthecove Zuletzt aktualisiert am 21.07.2015 - 17:57
Article

Debug SPI BIOS after Power Up Sequence

Describe how to halt CPU core, after power up sequence including CPU reset deassertion, to read/display SPI BIOS
Autor: Kan Hayashi (Intel) Zuletzt aktualisiert am 21.07.2015 - 08:55
Article

Using Intel MKL and Intel TBB in the same application

Intel MKL 11.3 Beta has introduced Intel TBB support.

Autor: Gennady Fedorov (Intel) Zuletzt aktualisiert am 09.07.2015 - 23:29
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