Xeon Phi, архитектура Knights Corner и улучшение пройденного

Authored by vilianov
Если делаешь что-то хорошо и с душой, оно обязательно сослужит тебе хорошую службу. Иногда сразу, иногда через годы. Но никогда, никогда хорошо сделанное не исчезает бесследно. Last updated on 23/08/2012 - 15:40

Cache Blocking Techniques

Authored by AmandaS (Intel)

Compiler Methodology for Intel® MIC Architecture

Last updated on 03/01/2014 - 11:24

Advanced Intel® Xeon Phi™ Coprocessor Workshop Memory Part 1: Basics

Authored by Jerry Makare (Intel)

Explicit and implicit memory models; advanced usages of each memory model, including asynchronous offload and buffering; BKMs to enable best performance of the memory hierarchy on KNC

Last updated on 06/09/2013 - 18:26

Advanced Intel® Xeon Phi™ Coprocessor Workshop Memory Part 2: Performance Tuning

Authored by Jerry Makare (Intel)

Explicit and implicit memory models; advanced usages of each memory model, including asynchronous offload and buffering; BKMs to enable best performance of the memory hierarchy on KNC

Last updated on 06/09/2013 - 18:26

Understanding MPI Load Imbalance with Intel®Trace Analyzer and Collector

Authored by Scott McMillan (Intel)
Download Article Last updated on 06/09/2013 - 18:26

Reaching Technology From Blogs 10

Authored by Jerry Makare (Intel)
James Reinders joins us this time to talk to us about a blog that introduces an article that he wrote about programming for Intel Xeon processors and the Intel Xeon Phi.
Last updated on 06/09/2013 - 18:26

Configuring Intel® Xeon Phi™ coprocessors inside a cluster

Authored by Michael Hebenstreit (Intel)

Author: Michael HebenstreitContributions: Romain Dolbeau, Jeremy C. SiadalVersion: 0.81, 20130110

Last updated on 06/09/2013 - 18:26