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Erweiterungen für die Intel Befehlssatzarchitektur

Intel® Xeon® Processor E5-2600 v3 Accelerates Hadoop HDFS Encryption
Von Mike Pearce (Intel)Veröffentlicht am 04/30/20150
The latest Intel® Xeon® processor with embedded Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) and the latest Cloudera distribution of Hadoop accelerate Big Data encryption. Herunterladen cloudera-aes-ni.pdf
AES-GCM Encryption Performance on Intel® Xeon® E5 v3 Processors
Von John Mechalas (Intel)Veröffentlicht am 03/30/20150
This case study examines the architectural improvements made to the Intel® Xeon® E5 v3 processor family in order to improve the performance of the Galois/Counter Mode of AES block encryption. It looks at the impact of these improvements on the nginx* web server when backed by the OpenSSL* SSL/TLS l…
Bringing SSL to Arduino* on Galileo Through wolfSSL*
Von John Mechalas (Intel)Veröffentlicht am 03/27/20150
A PDF version of this article, as well as a zip archive of the code samples, are available in the downloads section, below. Contents IntroductionGetting StartedStep 1: Building wolfSSL for YoctoStep 2: Installing wolfSSL On GalileoStep 3: Modifying the Compile Patterns for the Arduino IDEStep…
The Intel® Core™ M Processor
Von Colleen Culbertson (Intel)Veröffentlicht am 09/29/20140
This article, aimed at developers, will provide a glimpse into this 64-bit, multi-core SOC processor, with an overview of the available Intel technologies, including Intel® HD Graphics 5300.
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Intel® Virtualisierungstechnik (Intel® VT)

SDN, NFV, DPDK and the Open Networking Platform - FAQ
Von Colleen Culbertson (Intel)Veröffentlicht am 04/09/20150
Frequently Asked Questions on SDN, NFV, DPDK and the Intel® Open Network Platform Server Why are SDN and NFV so important? Software Defined Networking (SDN) and Network Functions Virtualization (NFV) are emerging as an alternative to traditional network design because they address many of the dra…
IDF'14 Software Networking Webinars
Von Mike Pearce (Intel)Veröffentlicht am 01/19/20150
DATS002 - Virtualizing the Network to Enable a Software Defined Infrastructure Intel is heavily investing in products and technologies for network overlays, network function virtualization (NFV) and software defined networking (SDN) to help drive the network hardware architectural transformation …
Open Source - OpenStack
Von adminVeröffentlicht am 12/19/20140
OpenStack OpenStack is a massively scalable, open cloud computing platform designed for deploying and managing public, private, and hybrid cloud solutions through a single control plane. This open-source project has evolved quickly and many early adopters, including Intel, are using it to orches…
Intel® Hardware Accelerated Execution Manager
Von adminVeröffentlicht am 10/24/201427
The Intel Hardware Accelerated Execution Manager (Intel® HAXM) is a hardware-assisted virtualization engine (hypervisor) that uses Intel Virtualization Technology (Intel® VT) to speed up Android app emulation on a host machine. In combination with Android x86 emulator images provided by Intel and t…
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Convertible EPT-violation #VE
Von ja1232
According to a number of Intel press and documentation, it seems that the Haswell processors should have the new processor feature that allows certain EPT violations to be converted to #VE (Virtualization Exception) so that these violations can be made without VM exits. I have looked into a number of different Haswell processors, but none of them has this support, i.e. bit 18 of IA32_VMX_PROCBASED_CTLS2 MSR is 0. This feature is not supported on for example i7-4770, i7-4790, i7-4940. Is this convertible #VE feature available on commodity processors yet? If so, which processors? Thanks!
Correct LOCK CMPXCHG emulation when the destination operand is in separate pages
Von Eugene K.0
How LOCK CMPXCHG instruction should be emulated if the destination operand crosses page boundary (and therefore can be in non-contiguous physical memory)? I see, KVM gives up emulation in this case:   static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, unsigned long addr, const void *old, const void *new, unsigned int bytes, struct x86_exception *exception) { ... if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) goto emul_write; ... return X86EMUL_CONTINUE; emul_write: printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); return emulator_write_emulated(ctxt, addr, new, bytes, exception); }   What is the approach for most correct emulation which is as close as possible to the native execution?  
How to enable virtualization in intel dual core processor E5400
Von Jonathan A.1
How to enable virtualization in intel dual core processor E5400 Please help me in doing this Mother board is DG41RQ
vt-d posted interrupts support
Von Rakesh B.1
Hello,         I have the S2600CP server board with cpu "Intel(R) Xeon(R) CPU E5-2620 v2 @ 2.10GHz" which supports for APICv, I had patched the linux kernel source 3.18.0 to support vt-d posted interrupts on direct assigned devices, Given in lkml "".         I had checked the vt-d specification document[1] that describes "Remapping hardware support for interrupt-posting capability is reported through the Posted Interrupt Support (PI) field in the Capability register (CAP_REG)", In which it returns as the posted interrupt is not supported.  The assigning the ixgbe network device is been done via VFIO assignment method.         [1]         Does the above hardware support vt-d posted interrupt for direct assigned device assignment or it requires any hardware to do this.   Thanks Rakesh
Intel VT-D and Intel X99 motherboards
Von Ward H.1
Hi, I am thinking of buying a X99 motherboard that I can use for Vmware Workstation. The two brands that I am thinking of are ASUS and GigaByte. I have been looking into the Virtualization and plan on running VMWare Workstation 11.  So virtualize windows Server 2012, Windows 8.1 etc. Plus VMWare ESXi. So I think for the last one I need Vt-d. Now I have notice the the ASUS MB's have a few more options for VTD like: Vtd Azalea VCp optimizations. Interrupt Remapping Coherency Support (Non-ISoch) Coherency Support (ISoch) However the GigaByte board only allows me to turn VT-d on and off. So since I can't control these options would they be on by default on the GigaByte, is there anything 'Disadvantage' I have not being able to control them? (Or is all this a bit of a non-issue ?) BTW - I can understand people here might not know specifically about VMWare or the motherboards in question. For example I am wondering if say a board supports VT-d means that these options are inclusi…
RSM and multiple cores
Von MP1
Hi all, I am trying to understand a technology that makes use of SMM in relation to hypervisors (hypercheck), and I have a number of questions about SMM in general - I hope I am posting in the right forum. I'd be interested to understand the following: 1) I know that on SMI asserting, all cores (at different interruptible boundaries) will enter SMM: are there spurious cases where SMM is triggered on only less cores? 2) The RSM instruction is said to return the processor to the not-SMM state. Does it need to be executed on every processor in SMM mode? 3) If I am in SMM mode with all my cores (i.e. I wait until them all are in SMM with a mutex), if I execute RSM from one core, does it resume normal operations (i.e. the kernel code it was executing) while the others are left in SMM mode? I am asking because the Default Treatment of RSM (33.14.2) is not exactly clear to me in Intel's doc.   Thanks in advance.    
DCBX on XL710
Von Chakravarthy N.1
Hi, I am trying to configure DCBX & ETS on Intel XL710 in Linux. Is it currently supported? dcbtool reports DCBX is not enabled and I could not find other any linux utility to configure ETS. Please let me know , if there is any config guide I can refer to to get it working. Thanks ~Chakri
Assign pages to VT-D devices
Von steven7653
Need some help understanding the theory of operation for implementing Vt-D.  I've been through the manual a couple of times.  The part I'm having trouble understanding is when we assign the page tables to the root complex structures.  How does the guest know which frames it's allowed to assign for DMA use?  The only work around I could think of is to either A do a VMCALL and ask, or B mirror the entire range the guest is allowed to access vie EPT and assign that to the root complex structure as well.     
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