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Intel® Identity Protection Technology with PKI - Technology Overview
By Jeff Kataoka (Intel)Posted 03/19/20130
Corporate enterprise, government entities, healtcare and more are looking to add additional security to protect access to their network and business information. Intel® Identity Protection Technology on the latest PCs with Intel® Core® vPro™ processor can be combined with authentication security so…
Deeper Levels of Security with Intel® Identity Protection Technology - White paper
By Jeff Kataoka (Intel)Posted 02/26/20131
White Paper: Deeper Levels of Security with Intel® Identity Protection Technology With the latest release in 2012 of Intel® Identity Protection Technology (Intel® IPT) introduced additional capabilities beyond the initial one-time password (OTP) solutions embedded in silicon and provided an extensi…
Technology Brief: Intel® Identity Protection Technology ( Intel® IPT )
By Jeff Kataoka (Intel)Posted 02/22/20130
Safeguard Sensitive Information with Intel® Identity Protection Technology ( Intel® IPT ) Guarding personal identities and online accounts has become a major concern for consumers, business, government and institution as the threat from hackers and malware grows.  Creating a simple, strong and secu…
Memory profiling techniques using Intel System Studio
By Naveen Gv (Intel)Posted 02/14/20130
Introduction One of the problems with developing embedded systems is the detection of memory errors; like Memory leaks Memory corruption Allocation / de-allocation API mismatches Inconsistent memory API usage etc. These memory errors degrade performance of any embedded systems. Designing and p…


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Intel® Virtualisierungstechnik (Intel® VT)

Intel® Virtualization Technology: Best Practices for Software Vendors
By Posted 02/02/20121
Overview As companies continue to strive to meet expanding goals with smaller budgets, they increasingly turn to virtualization as a means to consolidate servers. Successful reduction in server count by these means enables organizations to decrease capital expenditures in the form of equipment and …
To VT-D or Not to VT-D? A guide on whether to Utilize Direct Device Attach in your Virtualized System?
By Hussam Mousa (Intel)Posted 02/02/20121
Intel VT-D Direct Device Attach allows a Virtual Machine to control an entire PCI-E device (e.g. NIC) while bypassing any VMM interference. The performance benefit will be a dramatic reduction in CPU utilization, but the precise gain will vary.
Intel® Active Management Technology on Virtualized PCs: Expected behavior and Best Known Methods for using Intel® AMT with client virtualization
By Posted 02/02/20121
Abstract There are several key differences one must consider when using Intel Active Management Technology (Intel® AMT) features on a virtualized client. Those differences, along with Intel’s recommendations, are discussed in this article. It is important to understand those differences in order to…
Virtual World Server Power Savings by Dynamic Physics Tuning
By robert-adams (Intel)Posted 02/01/20124
Use of virtual worlds for training, entertainment, and collaboration is growing. Intel Labs has been researching the scalability of virtual worlds. This series explores some of the design, performance, and execution features of virtual world servers.


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Cross Compiling for Windows from Linux
By jrm@exa.com0
Not sure what forum would be most appropriate for this question, but this seemed close at least....kindly advise if there's a better place! For many years my company has been interested in the availability of cross compilation for Windows from Linux.   Our primary development environment is Linux, and the various approaches to getting linux buildable software to build on windows involve various levels of pain and suffering of one sort or another.   Being able to create native windows binaries without having to duplicate development environments would be a real benefit.   Some level of capability in this regard has been available via the MinGW tools for at least a decade, and we used it for a time, but limitations such as inability to debug with ordinary windows tools were too much of a hinderance.   Since we believe the claim that ICC is really the same compiler on Windows and Linux, it seems like it would be very straight-forward to create a Linux version of the compiler able to crea…
Trouble with 16-bit guest and SMM interaction
By Yogi D.1
I am writing a thin hypervisor that allows 16-bit mode guests.  The system boots into my 16-bit boot code which sets up 32-bit protected mode with identty mapped pages, then enables IA-32e compatibility mode and then switches into IA32e mode (64-bit).  In this mode, the software sets up a hypervisor to allow unrestricted guests (this includes setting up EPT with proper caching controls refecting the cache setup via MTRRs).  Then the software launches a 16-bit guest that runs well -- making BIOS calls for I/O services etc.  All this is working quite well. However, I noticed a small discrepency in behavior when I press the power button.  Before the 16-bit guest is launched, the system immediately shuts down when the power button is pushed.  This also happens when the host mode is active (i.e., my code is processing a VM Exit).  However, when the 16-bit mode guest is active, pushing the power button causes the machine to hang -- even the VM preemption timer does not cause a VM Exit. Beca…
intel vt-d for hvm
By Tommy F.1
Hello can someone explain why intel vt-d is required for HVM ( fully virtualized VM) and not for Para-virtualized VMs. I know that in the pci-passthrough, the VM has control of the PCI. so the PCI needs to do DMA access to the VM memory, but as this is not possible, the PCI will tell the IOMMU about the virtual address, which will be converted to the physcial address in RAM, which corresponds to the VM memory. But what happens in case of Para-virtualization VM?
Trouble handling host code programming errors via exceptions
By Yogi D.1
Hi.  I am writing a small OS-agnostic hypervisor as a teaching tool for my students.  The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots.  The hypervisor code switches to 32-bit proceted mode and then IA32e (64-bit mode, paged with identity mapping of linear -- physical addresses).  It then sets up the 64-bit exception handling mechanism and tests of this exception handling mechanism are successful (CPL and DPL are 0 so no stack switching is expected).  E.g., divide by 0, and page faults are handled as expected. Next, an IA32e mode guest is launched.  The guest has its own paging tables (these are not identity mapped).  The guest handles exceptions and interrutps by itself (i.e., it has a different IDT than the host, and the exception bitmap control is set to 0).  All this is working.  External interrupts, exceptions, memory accesses, access to I/O devices is working well int he guest.  The guest exits to the host because of vari…
Can we use Virtual Services in all Groups across the Software Development Life Cycle?
By David K.0
With the help of Virtual Services, we can start of the software development life cycle. But I have one question in mind can we follow in all Development like Custom, Website and Mobile Application Development?
where to get intel hd graphics driver for win 8
By icm k.1
how to intel hd graphic driver for core 2 duo processoer with win 8 os. Regards, Icmkarthi,          packers and movers in delhi  
Which Intel processor supports the new virtualization controls?
By prism17293
I am looking for some information on what processor supports new virtualization features. Specifically, I am interested in the following features: The numbers in paranthesis denote the bit position in the secondary processor execution controls - 1. EPT-violation #VE (18) 2. VMCS shadowing (14) 3. Enable VM functions (13) 4. Virtual interrupt delivery (9) 5. Apic register virtualization (8) I have a sandybridge (cpuid leaf1 returns family 0x6, model 0xa, stepping id 0x7) and it does not support the above features. Does anyone know of a current/future cpu that supports these features? Any help is appreciated. Thank you.
Question on VMentry Checks
By prism17291
During vmlaunch/vmresume, several checks are performed on the guest state area.  I was wondering if anyone else had noticed that Guest RSP field is never checked for a non-canonical address. The virtualization spec talks about such checks for Guest RIP or GDTR or IDTR. I was wondering why this check was not done for the Guest RSP?


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