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Accelerating ANSYS* Mechanical Structural Analysis with Intel® Xeon Phi™ Coprocessors
By pjbesl (Intel)Posted 03/13/20140
Abstract In 2013, using an updated Intel® Math Kernel Library (Intel® MKL), ANSYS added Intel® Xeon Phi™ coprocessor support with automatic offload (AO) to their ANSYS Mechanical software. The result was a 1.72X performance improvement1,2 over two CPU cores alone. For ANSYS developers, the changes…
Red Hat and Intel: Delivering Real Business Value for Cloud Computing
By DANIEL F. (Intel)Posted 03/12/20140
Download this 5-minute video featuring executives from Red Hat and Intel talking about the companies' joint efforts to deliver real business value for cloud computing.  Jim Totton is VP of the RHEL Business Unit at Red Hat, and Jason Waxman is the GM of Cloud Infrastructure at Intel's Data Center G…
Intel® Cluster Tools Open Source Downloads
By Gergana Slavova (Intel)Posted 03/06/20140
This article makes available third-party libraries and sources that were used in the creation of Intel® Software Development Products. Intel provides this software pursuant to their applicable licenses. Products and Versions: Intel® Trace Analyzer and Collector for Linux* gcc-3.2.3-42.zip (which…
Intel® MPI Library 4.1 Update 3 Build 049 Readme
By Gergana Slavova (Intel)Posted 03/06/20140
The Intel® MPI Library for Linux* and Windows* is a high-performance interconnect-independent multi-fabric library implementation of the industry-standard Message Passing Interface, v2.2 (MPI-2.2) specification. This package is for MPI users who develop on and build for IA-32 and Intel® 64 architec…

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Is there some books about SIMD(sse, avx and so on) optimization?
By zhang h.2
~Can someone please recommend a few books on program optimization? I use  multithreading and simd to improve the performance of the program. I always learn simd through the website, and ask questions in the web site. Now I want to buy some books to learn. Is there any books on simd ? Thanks
RTM abort due to RTM_RETIRED.ABORTED_MISC5
By le g.2
Hi there, I drop a piece of CPU-bounded code into the Linux Kernel with local interrupt disabled. The code is surrounded by RTM instructions. On average, the code commits successfully within around 100 tries. On abortion, the reason reported by PMU is RTM_RETIRED.ABORTED_MISC5  I wonder what would be the reason provided that the local interrupt has been disabled? PS. The description of RTM_RETIRED.ABORTED_MISC5: none of the previous 4 categories (e.g. interrupt). Thanks in advance. BR, Le Guan
MultiThreading with MKL library nonlinear least square solver
By Nikolay P.3
Hello everybody,  I am using the intel solution for Nonlinear Least Squares Problem with Linear (Bound) Constraintshttp://software.intel.com/sites/products/documentation/hpc/mkl/mklman/GUID-B6BADF1C-F90C-4D30-8B84-CF9A5F970E08.htm#GUID-B6BADF1C-F90C-4D30-8B84-CF9A5F970E08 Question: what do I need to do to run the optimizer in parallel? A. Let me consider the intel example ex_nlsqp_bc_c.c, let's say I just call omp_set_num_threads(n) before starting the minimization loop: omp_set_num_threads(n); //no pragmas!!! Just want to make sure I don't have to put any pragmas in the cycle. while(not_converged) {  dtrnlspbc_solve(OPTION);  //intel mkl function minimizer;    if(OPTION-1) {my_function();}  // user-supplied function else if (OPTION-2) {djacobi(my_function);} //intel mkl function (numerical gradient);   Does it call my_function from different threads? } In the multithreading mode what is done in parallel? Jacobian construction or just manipulations with Jacobian? I hope that  calls …
threading
By Divyesh2
I have intel i3 processor on my laptop. though it has 2 cores it can run 4 threads at a time. When I see task manager I see programs with 11 threads , 40 threads. How are these threads scheduled? is it hardware implemented or managed by the host OS?
Instruction set extensions programming reference, revision 17,
By Mark Charney (Intel)10
An updated instruction set extensions programming reference, revision 17, has been posted here.  It includes information about: Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions Intel® Secure Hash Algorithm (Intel® SHA) extensions  Intel® Memory Protection Extensions (Intel® MPX)  For more information about the technologies: http://www.intel.com/software/isa  
Intel® Software Development Emulator, Release 6.12
By Ady Tal (Intel)0
Hello, we just released version 6.12 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sde It includes: Support to Mac OSX version 10.9. Improved the TSX statistics information. Various fixes with the emulation of floating-point instructions of Intel AVX-512. Enabled the alignment checker tool by default for instructions that require alignment. Fixed mismatch between mix and dynamic mask profiler. Updated the Intel MPX runtime libraries for Windows.  Performance improvements when modeling a CPU prior to AVX-512.  
MOVNTI and alignment for real mode
By Kostik B.2
In the SDM rev. 48, vol. 2A, page 3-546, in the description of the exceptions for the MOVNTI instruction in the real-mode, it is specified that the instruction can generate #GP If a memory operand is not aligned on a 16-byte boundary, regardless of segment. There is no exceptions specified for unaligned stores for protected or long mode, except for AC enabled.  AMD reference is also silent about the unaligned stores.  Is this indeed an irregularity in real mode, or just a typo in the spec ?
I have come to an interresting subject
By aminer100
Hello... I have come to an interresting subject, as you have noticed i have designed and implemented parallel programs that you can find in my following website: http://pages.videotron.com/aminer/ But i was thinking more and more about my parallel programs,and asking myself some questions... if you take a look carefully at my compression library or my parallel archiver you will notice that this compression libraries are construtions of easier high level objects that you can use to do your compression EASILY, it's like robotics and automatization , now you are not required to write compression algorithms or write those high level objects that easy for you the compression process, you are only required to call the methods of those high level objects that do the compression for you, so it's like robotic automatization, you are only required to instantiate high level objects that do the compression and call the methods and it is much easier, but since it's like robotic automatizatio…

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