Scalable parallel genetic algorithm for identifying sequences construction

The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads.

Parallel fault simulation algorithm for multi-core systems with common memory

Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.

Courseware - Object Oriented

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Parallel Java* Course: From Thread to Cloud

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  • Designing Artificial Intelligence for Games (Part 4)

    The gaming industry has seen great strides in game complexity recently. Game developers are challenged to create increasingly compelling games. This series explores important Artificial Intelligence (AI) concepts and how to optimize them for multi-core.
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  • GDC09: How Intel Parallel Studio works

    During the second day at Game Developers Conference 2009 in Cologne we had the chance to have a closer look at Intel Parallel Studio. Edmund Preiss took some time and shared some insights with us. OK, I wrote nearly anything about Parallel Studio but with this video blog have the chance to get all relevant information about Parallel Studio.

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