platform monitoring

Documentation for uncore performance monitoring units

Hello everyone,

The uncore performance monitoring units (uncore PMUs) provide many useful information like memory controller traffic, traffic between sockets/processor packages, energy related metrics in the uncore (sleep states for Intel® Quick Path Interconnect links or DRAM sleep states for example). These metrics can be used in tools for system and platform analysis.

Merrifield Uncore Performance Monitoring Events

Using the Merrifield SoC Performance Monitoring Events

This article focuses directly on the uncore performance monitoring events for the SoC Merrifield.  For the introduction to SoC uncore performance monitoring, please see this article:

Introduction to the Merrifield SoC

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  • Rangeley Uncore Performance Monitoring Events

    Using the Rangeley SoC Performance Monitoring Events

    This article focuses directly on the uncore performance monitoring events for the SoC Rangeley.  For the introduction to SoC uncore performance monitoring, please see this article:

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  • Baytrail Uncore Performance Monitoring Events

    Using the Baytrail SoC Performance Monitoring Events

    This article focuses directly on the uncore performance monitoring events for the SoC Baytrail.  For the introduction to SoC uncore performance monitoring, please see this artictle:

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  • Silvermont SoC Uncore Performance Monitoring Guide

    Welcome to the System on a Chip (SoC) uncore performance monitoring guide. 

    This article will introduce you to the SoC uncore performance monitoring event set and provide details on the events and how to interpret results.

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  • Platform Monitoring

    Welcome to Intel Platform Monitoring Community!

    Here you will find information covering performance monitoring and software tuning, and platform monitoring topics. Performance monitoring covers a variety of topics including an introduction to monitoring and software tuning methodologies, as well as software optimization techniques and best know methods (BKMs) for novice and more advanced users.

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  • Black Belt Itanium® Processor Performance: Performance Monitoring Capabilities (Part 2 of 5)

    by David Levinthal


    Introduction

    This paper, second in a series of five articles on optimizing Itanium® processor family software, focuses on the unprecedented performance monitoring capabilities of the Itanium® processor. The future articles will cover data blocking and multi level caches, the use of opcode matching and data ear events in performance analysis, visual inspection of assembler in the Intel® VTune™ analyzer and a variety of other topics. See the other parts of this series for more information:

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