1.5 days of “Intel HPC Developers Conference” just before SC15 (in Austin)…November 14-15

1.5 days of “Intel HPC Developers Conference” just before SC15 (in Austin)…


http://hpcdevcon.intel.com   <<< everything you need to know about the conference including how to register!

New tool available in beta: Vectorization Advisor

Software must be both threaded and vectorized to get the full performance benefit from today’s and tomorrow’s hardware.  Vectorization Advisor is a vectorization analysis tool that lets you identify loops that will benefit most from vectorization, identify what is blocking effective vectorization, explore the benefit of alternative data reorganizations, and increase the confidence that vectorization is safe.  

Vectorization Advisor is now available for beta test as a part of Intel® Advisor XE 2016. 

The Intel® Parallel Studio XE 2016 Beta program is now available!

Intel Parallel Studio XE 2016 is being made available now as part of a beta test program. In this beta test, you will have early access to Intel® Parallel Studio XE 2016 products and the opportunity to provide feedback to help make our products better. Registration is easy through the pre-Beta survey site

This suite of products brings together exciting new technologies along with improvements to Intel’s existing software development tools:

Troubleshooting HOWTO: Bad hardware? MPSS? Configuration?

Are you having problems with your hardware (Cannot see your Intel(R) Xeon Phi(tm) coprocessor?  Sporadic accessibility?) or with the Intel(R) Manycore Platform Software Stack (Intel(R) MPSS) running reliably?

Attached to this post are PDF "flowcharts" that explain how you can troubleshoot the problem (note:  Both Linux and Windows flowcharts are available), and shows what information you will want to collect if you need to escalate your issue to your OEM provider or Intel.

What collateral/documentation do you want to see?

Do you have questions that you are not finding the answers for in our documentation?  Need more training, source code examples, on what specifically?   Help us understand what's missing so that we can make sure we develop documentation you care about (what is important, and what is nice to have)!   Thank you

FAQS: Compilers, Libraries, Performance, Profiling and Optimization.

In the period prior to the launch of Intel® Xeon Phi™ coprocessor, Intel collected questions from developers who had been involved in pilot testing. This document contains some of the most common questions asked. Additional information and Best-Known-Methods for the Intel Xeon Phi coprocessor can be found here.

The Intel® Compiler reference guides can be found at:

Offload compiler (and Linker/Librarian) option docs

Using Intel Fortran or Intel C++ documentation tells you how to pass on options to the offload compiler, linker, etc... components, but it does not list the options available for each component. Nor does it have a link or other indication as to were to locate the documents. Can someone point me in the direction of these documents (and can the user documentation be updated to contain this information and/or links to this information).

Jim Dempsey

Using global pointers to allocate memory on the MIC and reusing it

Hi all,

I am using the offload programming model for my project. What I have is a global pointer that I use to allocate memory on the MIC. After doing some more computation on the host I then try to copy the results from host memory to the memory in the MIC using in() for host structure and nocopy() for the global pointer. The documentation and a few of the forum posts say that it should work however in my case it results in a segfault.

What I read:

Unix* abonnieren