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MPSS latest build, 3.4.2 source, does not compile

I tried doing a Make on the linux driver module, linux-2.6.38+mpss3.4.2, and I get an error message, that intel_i2c.c, does not compile:

/home/aweiss/mpss/mpss-3.4.2/build/linux-2.6.38+mpss3.4.2/drivers/gpu/drm/i915/intel_i2c.c:269:2: error: ‘dev_priv’ undeclared (first use in this function)

dummy_read_dbox_regs()
{
        I915_GMBUS_READ(DBOX_ADAK_CTRL_REG);
        I915_GMBUS_READ(DBOX_SW_FLAG_REG);
}

scif_connect fails

Hi Folks

I am currently writing a simple program with the SCIF API.

My current goal is it to allocate a buffer on the Host node, send it over to the MIC and send it back.
Sounds pretty simple but I am currently failing with scif_connect as it fails all the time.

I know that the lenght of a message for the scif_send and scif_recv should not be long but I wanted to try it this way first before i get to RDMA.

Hopy anyone can help me and tell my why my Program is failing.

 

Thanks in advance

PCIe Root Complex and the PCH

Hello All,

First of all, sorry this is not in the appropriate forum but I was directed to post this here.

I have a question that's been bugging me regarding the PCIe Root Complex and the PCH and I'm hoping someone will be able to help clear things up a bit.

I've always presumed that the PCIe Root Complex was a combination of the CPU and the PCH as they both contain PCIe Root Ports, thereby connecting PCIe devices to CPU/memory. 

Scalable Parallel implementation of Conjugate Gradient Linear System solver library that is NUMA-aware and cache-aware

Hello,

My Scalable Parallel implementation of Conjugate Gradient Linear System solver library that is NUMA-aware and cache-aware is here, now you
don't need to allocate your arrays in different NUMA-nodes, cause i have implemented all the NUMA functions for you, this new algorithm
is NUMA-aware and cache-aware and it's really scalable on NUMA-architecture and on multicores, so if you have a NUMA architecture just run the "test.pas" example that i have included on the zipfile and you will notice that my new algorithm is really scalable on NUMA architecture.

Performance: offload vs native mode and Fortran module

Hi,

System: Centos 7.0, compiler: parallel_studio_xe_2015, MPSS 3.4.2.

I have Fortran code, when I compile in native mode. The running time is about 2.4 (seconds).  When I compile in offload the running time is about 5.2 (seconds). The transfer data size back to CPU in upload mode is about 144MB, which I estimated  is about 0.024 (seconds)  for  6GB/s PCI Express. The data for offload from CPU to Xeon Phi is about 3.6MB. My question is why the offload code is much slower than the native mode code? To compile the offload code I run

Physical server provisioning with OpenStack*

This article explores the internal details of provisioning a physical machine using OpenStack*. Steps for setting up OpenStack are included, and no special hardware is required to begin use. If you already use OpenStack, follow these instructions using the hardware you currently have. If you are new to OpenStack, you will need a commodity access switch and two physical servers with ports connected to a switch that is on the same VLAN or broadcast domain.

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