An Intro to MCDRAM (High Bandwidth Memory) on Knights Landing

Intel’s next generation Xeon Phi™ processor family x200 product (code-named Knights Landing) brings in new memory technology, a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in addition to the traditional DDR4. MCDRAM is a high bandwidth, low capacity memory, packaged with the Knights Landing Silicon.

SGX - is HeapMaxSize necessary?

The .edl files contain a HeapMaxSize entry. The SDK User Guide states that this is because

Enclave memory is a limited resource. Maximum heap size is set at enclave creation.

But doesn't the SGX specification allow EPC page swapping (EPA, EBLOCK, ETRACK, EWB)?

Or in a more practical sense: is there a disadvantage to setting HeapMaxSize=2^64 Bytes?

Maybe EPC page swapping is not yet supported by the SDK, or maybe the trusted enclave code has to manually trigger such swapping?

Linux does not detect Xeon Phi card

Here is our setup:

Motherboard: Asus P9X79 WS BIOS version 4802 (Above 4G decoding is enabled)
CPU: Intel Core i7 4820K
OS: CentOS 7.1 with Linux 3.10.0-229

I have a Xeon Phi 31S1P. I have not been able to display the card
with lspci. I have tried to put in a different PCI slot. I have
upgraded the BIOS of the motherboard to the latest version. I have
tried passing noapic and pci=realloc to the Linux kernel. Nothing
seems to work.

I do not have a Xeon processor. Could that be the problem?

Below is the complete dmesg output.

Intel SGX with i5-6300U processor

CPUID[07H][EBX][bit 2] reveals that SGX feature is unavailable with the i5-6300U processor I am using, but the specification < indicates that Intel SGX is available with the processor.

Should I install the evaluation SDK first? I am with Windows 10 Pro now.

CPUID dump

Message Address Register: Redirection hint & Destination mode

Intel® 64 and IA-32 Architectures Software Developer’s Manual
Volume 3 (3A, 3B, 3C & 3D): System Programming Guide

I have a question about the combination of RH bit and DM bit of 10.11.1 Message Address Register Format.

I use the combination as below, it looks like work is going well.
RH = 0
DM = 1

But, there are following mentions in 10.11.1, so the combination of RH = 0 and DM = 1 looks like the wrong combination.

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