Intel® Streaming SIMD Extensions

What is syntax for broadcast decorator?

The ISE doc only describes the decorator syntax with the single example {1to16} (document 319433-022 page 7).

I would assume that generally you write {1ton} where n = the full vector size / the single element size.  But it would be nice to specify this exactly.

However, GNU `as` will not accept {1to4] or smaller.  Furthermore, it does not accept a broadcast decorator with a 128- or 256-bit vector size.  If I use .byte to assemble 128- and 256-bit instructions, the disassembler shows the {1to8} or {1to16} decorator regardless of VL.  Example:

IRET Pseudo-code Bug


I believe that there is a documentation bug in the pseudo-code for the IRET instruction in the current edition of Volume 2A of the Architectures Software Developers' Manual.

The case we're looking at is using IRET to switch from Ring-0 to Ring-3.

The prose for protected mode states:

New extension needed for Maps and Sets


In current SW lot of time every app is spending walking Maps and Sets (besides arrays, those are most often used data structures). I think this is place where CPU can provide enormous acceleration with specialized design and instructions for these data sets. Here is one idea how to do it:

Encodings for instructions with {sae} are unclear in the doc

Chapter 4.6 indicates that EVEX.L'L is encoded for the vector length, and that {sae} is supported for all vector lengths.

However, the various instruction pages, such as VCMPPD, only show {sae} for 512-bit vectors.  Furthermore, the E2 #UD equations indicate that EVEX.L'L must be 10b (VL=512).

Processor Trace decoding support library for Atom

Dear Intel guru,

Could I ask will libipt on github support decoding small-core (Atom) processor trace packets (pt pkt)?
Or is already supported in other commercial  product like PAL (Platform Analysis Library)?

I found that the Intel SDM documented the ia-core pt pkt format and atom processor (Cherry Trail) use another packet format documented in real-time-instruction-trace-atom-reference.pdf.

If I am wrong about there are two pkt format among ia and small core, please correct me.



Thank you!

Ooops - wrong instruction description in volume 2 of the SDM

Looking at the new version of Volume 2 of the SDM (document 325383-055), I just noticed that the "Description" field for the VINSERTF128 instruction (page 4-514) is incorrect.  It appears to have been copied (with some modification) from the description of the VINSERTPS instruction (which is described with the INSERTPS instruction on page 3-422), but it should be almost identical to the description of the VINSERTI128 instruction on page 4-515.

MPX instructions not in the Appendix A opcode map


In the last release 55  of  Intel® 64 and IA-32 Architectures Software Developer’s Manual in Vol 2C A-11, we can't see MPX instructions. In fact, I usually use opcode maps to find instructions encoding. I am not sure this forum can be used to report typos like these. Just tell me if I am not in the right place.



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