Intel® Streaming SIMD Extensions

Accelerating texture compression with Intel® Streaming SIMD Extensions

Improving ETC1 and ETC2 texture compression


What is texture compression?

Texture compression has been used for some time now in computer graphics to reduce the memory consumption and save bandwidth on the graphics pipeline. It is supported by modern graphics APIs, such as OpenGL* ES and DirectX*. The process of compressing a texture is lossy. Existing algorithms must not only achieve the best speedups but also preserve as much of the original information as possible.

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  • AVX512 for mobile?

    OK, so Skylake has been out for a month, and IDF is long past - but I still don't have an answer to one basic question: will there be any mobile chips that support a AVX512? At first my hopes had been dashed with the announcement that AVX would only be in available on Skylake Xeon, but then they were raised again when we found out that there would be a mobile Xeons for Skylake. 

    IA-32e 64-bit and compatibility mode


    From Intel developer manual I see

    IA-32e mode allows software to operate in one of two sub-modes:

    •          64-bit mode supports 64-bit OS and 64-bit applications
    •          Compatibility mode allows most legacy software to run; it co-exists with 64-bit applications under a 64-bit OS

    I have a quad-core with HT enabled i.e. 8 logical cores

    With KVM I want to run 32 bit and 64 bit VMs on a 64 bit Host OS. I want to allocate resources as follows

    Intel® X86 Encoder Decoder (Intel® XED) - new release site


    Until mid-2015, Intel XED had been distributed externally via Pin kits. However, with a recent change to Pin's C-runtime, it is now required that users of Intel XED obtain Intel XED compiled against a conventional C-runtime from a new site. The Intel XED library that comes with Pin is compiled only to work with the Pin C-runtime and not the standard runtime libraries available on every system. 

    The new site for distributing Intel XED is: 

    What is behavior of LD + OP instruction with register source and EVEX.b = 1?

    I'm confused about whether EVEX.b = 1 is allowed (and ignored) for instructions such as

    VPMINUD reg, reg, reg

    I cite this case because the gnu assembler testsuite has a case with this instruction but b = 1.  objdump disassembles the instruction without respect to the value of b.

    If the third operand is memory, then it can have {b32/64} attached and the value of b is significant.  But with a register, there is no exception or rounding inherent in the operation, so the value of b shouldn't matter.

    Massive speedup of integer SSE2 code using AVX1(!)


    I've recently recompiled an old C program which mainly uses integers, with VC 2013 and ICC 13.1 compilers and was initially compiled targeting SSE2 architecture using VC 2010 compiler.

    I targeted AVX (version 1.0) architecture in the compiler options for my SandyBridge and I saw a massive speedup of 68% with both compilers (VC 2013 and ICC 13.1) compared to old SSE2 optimizations.

    I recompiled the C code targeting this time AVX2 for my Haswell but the speedup was the same like AVX for Haswell for both compilers.

    My questions:

    Intel SDE and PIN doesn't work on Win10 on a VS2015 compiled app


    trying to running an application with Intel SDE 7.21.0 tool which includes newest pin tool Pin 2.14 kit 72480 but still don't know if because Windows 10 RTM or app compiled using VS2015 RTM get an error:

    Pin 2.14 kit 72480
    E:  DBG_TRACE: Unexpected debugging event: EXCEPTION_DEBUG_EVENT: ExceptionCode  = 0xc0000005, ExceptionAddress = 0x77a81243, Instruction = 418b01a9f8fffeff0f85a40000002501
    E:  Incompatible operating system or incompatible software installed on the system
    E:  Pin is exiting due to fatal error

    Intel® Streaming SIMD Extensions abonnieren