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Further information about different barrier algorithms


I'm researching on barrier algorithms using SIMD instructions and I'm trying to deeply understand the different versions included in the RTL.

I've noticed that there is a new barrier algorithm (hierarchical) since the last time I had a look.

Where could I find a further description of them? Could someone from Intel provides me with further information?


Thank you in advance.

Kind regards.

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts. With the log data from the Intel SDE you can diagnose cache set population to determine if there is non-uniform cache set usage causing capacity overflows. A refined log data may be used to further diagnose the source of the aborts.

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    an interesting and serious topic

    Hello there:

             I have found an interesting  appearance which I can not explain. Okey, let's go.

             I apply "micsmc" to surveiling the offload running state of MIC. The critical code like this:

    #pragma offload target(mic:0) inout(XXXX) in (XXXX)
    #pragma omp parallel for schedule (dynamic)
    for( int i = 0; i < num_cluster; i++) // num_cluster from 60 to 300,concentrated on 90~150
      do something....

             And then set the environment variables :

    export OMP_NUM_THREADS=X
    export KMP_AFFINITY=compact

    Open Source abonnieren