Open Source

Meshcentral - Quick update

In the past week or so, my co-workers and myself have been doing a lot of bug fixing and getting ready to release a bunch of new features. So, in general, working is moving along very well. I released a bunch of server updates yesterday on the info.meshcentral.com web site including a new version of the server installer.

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这个秋天,英特尔为全球开发者社区带来10场物联网创客马拉松活动。

如果您是创客,物联网创业企业,开发者,高校师生或是硬件初学者,快来加入我们,领取免费的开发套件实现你的物联梦想!除了为您提供开发套件外,我们还为参与者准备了各种开发工具(如额外的传感器、3D 打印机等),美味的食物,现场礼品及最佳物联网方案的奖金!快来体验基于英特尔架构并与 Arduino* 软硬件兼容的开发套件,配套传感器,软件和附件来激发你的创意!

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  • Integrating APIs with XDK - FoodEssentials Sample App

    Download Intel XDK and sign up for an Intel XDK account > find this app under Start A New Project > Work with a Demo or find the source code for this sample app here: https://github.com/gomobile/sample-mashery-foodessentials

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  • Meshcentral - Improved Android Agent + Mesh Security Update

    The mesh team has been hard at work and this week it’s Rick Edgecombe’s turn to shine with his release of the latest Mesh Agent for Android on the Google Play store. The improvements touch many aspects of the Android agent and so, we will have to look at this in detail:

    mfense question.

    Want to know in X64, does mfence  instruction flush the CPU cache globally, meaning :-

    If CPU0 does mfence, then does it invalidate its cacheline which contain the shared memory location, which is updated at CPU1. And it also results in CPU1 flush its cache containing that shared memory location ?

    In other words, if CPU0 does mfence, is it going to get the correct shared memory content which is updated at CPU1 ? Or CPU1 which has updated the shared memory, need to do mfence ? 

    Thanks a lot

     

    New code release

    We are excited to announce the next release of the Intel® OpenMP* Runtime Library at openmprtl.org. This release aligns with Intel® Parallel Studio XE 2015.

     

     

    New Features

    • Contribution from ScaleMP: stack padding.
    • Redesign of wait and release code; performance improvements.

    Bug Fixes

    Управление режимами вычислений с плавающей запятой при использовании Intel® Threading Building Blocks

    В Intel® Threading Building Blocks (Intel® TBB) 4.2, обновление 4, появилась расширенная поддержка управления параметрами вычислений с плавающей запятой. Теперь эти параметры можно указать при вызове большинства параллельных алгоритмов (включая flow::graph). В этом блоге мне бы хотелось рассказать о некоторых особенностях, новых функциях и общей поддержке вычислений с плавающей запятой в Intel TBB. Этот блог не посвящен общей поддержке вычислений с плавающей запятой в ЦП.

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