When the user develops multithreaded applications, the user should protect critical (sensitive) code area called by threads, so threads access shared memory without data conflict. Most of time, the user might use critical_section, mutex, semaphore, atomic, events, or other “locks” to protect critical code area and let them not re-enterable.
How about the future? Have we reached the pinnacle of power management?
Using Intel® GPUs to Optimize the Performance and Power Consumption of Total Immersion's D'Fusion* Augmented Reality Pipeline
Michael Jeronimo, Intel (email@example.com)
Pascal Mobuchon, Total Immersion (firstname.lastname@example.org)
Recientemente publicamos la “Guía instructiva para Windows* 8: cómo escribir una aplicación multiproceso para Windows Store* con Threading Building Blocks de Intel®”. En esa guía dijimos que el motor de cálculo paralelo se puede portar fácilmente a otras plataformas móviles o de escritorio. Android es un buen ejemplo de ese tipo de plataforma móvil.
Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits. Intel AVX brought 256-bits floating-point SIMD instructions, but it didn't include 256-bits integer SIMD instructions. Intel AVX2 allows you to operate with the AVX 256-bits wide YMM register for integer data types. In this post, I’ll explain how developers can speedup big data processing with the new 256-bits integer SIMD instructions.
Power management policy has evolved over the years. The earliest policies consisted of little more than some critical temperature sensors and an interrupt routine that attempted (often unsuccessfully) to cleanly shut down the system before something really bad happened.
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.
I have talked incessantly over the years about power states (e.g. P-states and C-states), and how the processor transitions from one state to another. For a list of previous blogs in this series, and well as other related blogs on power and power management, see the article at [List0]. But I have left out an important component of power management, namely the policy.
(For a PDF version of this article, download the attachment.)