Intel ISA Extensions

Resources about Intel® Transactional Synchronization Extensions (Intel TSX)

Hi,

you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsx

By a suggestion from some senior forum contributors I am making this post sticky.

Best regards,

Roman

Links to instruction documentation

No explanation of comparison codes for integer vectpr compare instructions

In the ISE document 319433-022, instructions such as VPCMPD refer to an imm8 operand as a comparison predicate.  However, there is no explanation of the values of the predicate.

The Operation section of the instruction doc does indicate the 8 values of the low 3 bits.  But I only noticed this by chance.  It would be nice to have something in the Description section to refer the reader to the details.  Actually, why not use a similar language to that for VCMPPS, etc.

Wrong memory size for VGATHERQPS (?)

My version of the document, 319433-022, page 350 shows

EVEX.128.66.0F38.W0 93 /vsib
VGATHERQPS xmm1 {k1}, vm64x

I think this should be vm32x, not vm64x, since the operands are single-precision floats.

Similarly for the other two encodings of this instruction.

Please check other gather/scatter instructions that they are correct also.

 

What is syntax for broadcast decorator?

The ISE doc only describes the decorator syntax with the single example {1to16} (document 319433-022 page 7).

I would assume that generally you write {1ton} where n = the full vector size / the single element size.  But it would be nice to specify this exactly.

However, GNU `as` will not accept {1to4] or smaller.  Furthermore, it does not accept a broadcast decorator with a 128- or 256-bit vector size.  If I use .byte to assemble 128- and 256-bit instructions, the disassembler shows the {1to8} or {1to16} decorator regardless of VL.  Example:

IRET Pseudo-code Bug

Hi,

I believe that there is a documentation bug in the pseudo-code for the IRET instruction in the current edition of Volume 2A of the Architectures Software Developers' Manual.

The case we're looking at is using IRET to switch from Ring-0 to Ring-3.

The prose for protected mode states:

New extension needed for Maps and Sets

Idea:

In current SW lot of time every app is spending walking Maps and Sets (besides arrays, those are most often used data structures). I think this is place where CPU can provide enormous acceleration with specialized design and instructions for these data sets. Here is one idea how to do it:

Encodings for instructions with {sae} are unclear in the doc

Chapter 4.6 indicates that EVEX.L'L is encoded for the vector length, and that {sae} is supported for all vector lengths.

However, the various instruction pages, such as VCMPPD, only show {sae} for 512-bit vectors.  Furthermore, the E2 #UD equations indicate that EVEX.L'L must be 10b (VL=512).

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