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Entwickler aufgepasst: Nutzen Sie die Vorteile von Intel® VT. Tauschen Sie sich im Forum mit unseren Bloggern aus und teilen Sie uns mit, was für Sie wichtig ist. Lassen Sie uns wissen, was für Sie Erfolg bringend ist und wie wir Sie mit dieser Site und den enthaltenen Tools bei Ihren Bemühungen unterstützen können.

  • Erste Schritte
    • Intelligent Queueing Technologies für die Virtualisierung Neu & weiterhin relevant
    • Einführung zur Virtualisierung Neu
    • Glossar der Virtualisierungstechniken
    • Nutzungsmodelle der Virtualisierung
    • Lernprogramm: Erstellung einer virtuellen Maschine auf VMware*
    • Weshalb Virtualisierung für Softwarehersteller ein wichtiges Thema ist
    • Intel® Virtualisierungstechnik für Directed I/O (VT-d): Erweiterung von Intel Plattformen für die effiziente Virtualisierung von I/O-Geräten

    • Einige hilfreiche Abkürzungen

      ATA Application Targeted Accelerators
      BMC Baseboard Management Controller
      Boxboro Plattform für Nehalem EX (Intel® Xeon® 7500er Prozessoren und Tukwilla)
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables (Erweiterte Seitentabellen)
      ESI Enterprise Southbridge Interface
      EX Expandable Server (Ausbaufähiger Server)
      FBD Fully Buffered DIMM (Voll gepufferte DIMM)
      GT/s Giga-Übertragungen pro Sekunde
      HA Home Agent in QPI-basierten Systemen
      ICH IO Controller Hub
      IMC Integrated Memory Controller (Integrierter Memory-Controller)
      IOH IO Hub
      L1, L2 Level-1 bzw. Level-2-Cache
      LA Land Grid Array (Chip-Bauweise)
      LLC Last Level Cache (auf jedem Chip) oder Longest Latency Cache
      MC Mission Critical oder Multicore
      MC Memory Controller
      ME Manageability Engine
      NM Node Manager (Knotenmanager)
      NUMA Non-Uniform Memory Access
      OEM Original Equipment Manufacturer (ursprünglicher Gerätehersteller)
      PCI Peripheral Component Interface (Spezifikation)
      QPI Quick Path Interconnect (Punkt-Punkt-Verknüpfungen)
      RAS Reliability, Availability, Serviceability (Zuverlässigkeit, Verfügbarkeit, Servicefähigkeit)
      RMCP Remote Monitoring and Control Protocol (Remote-Überwachungs- und Kontrollprotokoll)
      SCTP Stream Control Transmission Protocol (Stream Control-Übertragungsprotokoll)
      SDDC Single Device Data Correction (Datenkorrektur Einzelgerät)
      SKU Stock Keeping Unit (d.h. Produktvariante)
      SMB Scalable Memory Buffer (Skalierbarer Memory-Puffer)
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface (Skalierbare Memory-Schnittstelle)
      SMT Threads Simultane Multithreading-Threads auf Hardware-CPUs auf jedem Kern (2 aktiviert, 1 nicht aktiviert)
      SSExy XY-Generierung von Vektorbefehlen (Streaming SIMD Extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module („Trusted“ Plattformmodul)
      TPV Third Party Vendor (Drittanbieter)
      Turbo Technik, die eine höhere Frequenz auf einem oder mehreren Kernen ermöglicht
      TXT Trusted Execution Technology
      Tylersburg Plattform für Nehalem EP (Intel® Xeon® 5500er Prozessoren) und Westmere EP(Intel® Xeon® 5600er Prozessoren)
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registering vm_exit handler in VT-x
Von ivan i.1
Hi all, I would like to ask how an VM_EXIT handler is registered in VMCS - could you give some example. As far as i know VM_EXIT handler is routine, it could  be defined as C function. My question is how to register that handler function and to trap VM_EXITs into that function. Could you give some API  or snippet.  I have one more question ... when the VM_EXIT  handler is register and the execution meets the VM_EXIT conditions what is the mechanism of invoking the VM_EXIT handler? Is the invoking of the registered VM_EXIT handler is performed by VT-x at hardware level or there is something more to be done? Best Regards
EPT cause triple fault
Von Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo
EPT Violation On a PTE free
Von Saptarshi S.2
 Hi All,        Is it possible to configure EPT Entries or VMCS such that whenever a guest frees a page the host can instantaneously become aware of this. I have checked out the intel software developer manual 3B. But the closest I could  get is by causing a write violation in the EPT paging structure. But again, it did not seem proper as such writing violation can arise because of many other reasons as well. Besides, the whole performance of EPT would be destroyed if the guest does cache-writethrough.      I was testing this stuff with KVM and I could see that the host is not aware of  deallocations that  take place in the guest after allocations. Regards Saptarshi Sen        
Ambiguity with CR3-store/load exiting settings
Von Eugene K.2
I have Intel(R) Core(TM) i5-2500 CPU. RDMSR on IA32_VMX_PROCBASED_CTLS MSR gives allowed-0 settings 0x0401E172, allowed-1 settings 0xFFF9FFFE. This means bits 15 (CR3-load exiting) and 16 (CR3-store exiting) of Primary Processor-Based VM-Execution Controls must be 1. However I can set them to zero and no any invalid VM entries happen. Why? CPU details: processor       : 0vendor_id       : GenuineIntelcpu family      : 6model           : 42model name      : Intel(R) Core(TM) i5-2500 CPU @ 3.30GHzstepping        : 7microcode       : 0x26cpu MHz         : 1600.000cache size      : 6144 KBphysical id     : 0siblings        : 4core id         : 0cpu cores       : 4apicid          : 0initial apicid  : 0fpu             : yesfpu_exception   : yescpuid level     : 13wp              : yesflags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl x…
Intel VT-x and VT-d for app development
Von Muhammad Khawar N.1
Hello, all! First some background on the situation:So, I'm going to be buying a new laptop soon, and one of my priorities is to do Windows Phone and Android app development on it. I don't play games, etc. so a high-end graphic chip is not my requirement. I need to run CPU-intensive simulation software like MATLAB occasionally so I need a good processor. Considering my budget and requirement and availability in my country; I've narrowed it down to two machines. An HP ProBook (which has an i7-3632QM processor + 8GB RAM), and an HP Pavilion (which has an i7-4702MQ + 4GB RAM). Now for the problem. Since I'll be doing app development, a good testing procedure is to test it on an emulator, for phone WP8 and Android... To run the emulators smoothly it is required that the processor support Intel Virtualization, and SLAT. Both processors do have Virtualization, but there is something called VT-d which is there for the Ivy Bridge but not the Haswell chip.  My questions are:1. Do I need VT-d fo…
VT-d hardware support on chipset Z87 (DH82Z87)
Von Bogdan B.5
There seem to be some inconsistency on ARK product reference site: This document Compatibility with Intel® Virtualization Technology (Intel® VT) ( specifies that chipset Z87 (DH82Z87) supports VT-d:   The following Intel® Desktop Boards support Intel VT with Directed I/O:   ChipsetDesktop Board H87, Q87, Z87 - DH87MC, DH87RL, DQ87PG, DZ87KLT-75K and the chipset product page here says:   "Intel® Virtualization Technology for Directed I/O (VT-d) ‡ No". Please confirm if this chipset supports this virtualization feature. Thanks,Biv 
VT-d programming
Von Yogi D.2
I am trying to expriment with DMA remapping using VT-d.  By reading the VT-d spec, I know how to setup the remapping tables.  However, I don't know how to locate the register that will receive the base address of the remapping table hierarchy. Reading the spec for my processor, I see there is a Root-Entry Table Address Register ( RTADDR_REG) at offset 20–27h.  But what is the base of this "block" ( the spec says this is PEG/DMI VT-d Remapping Engine Register Address Map). Can anyone help me find this in the documentation somehwhere?  Thanks!
DPDK Question
Von Alexey I.1
Hi to everyone! A couple of questions about DPDK: 1. Can Intel DPDK work with double tagged ethernet frames? To read frame with 2 tags and to write frame to the wire with two tags (QinQ technology) 2. Can Intel DPDK read and write MPLS tags?
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Aktive Forumsteilnehmer

David Ott: David ist Senior Software Engineer in der Intel Software Solutions Group. Derzeit arbeitet er an verschiedenen Aspekten des Enterprise-Computing, darunter Virtualisierung, Energieeffizienz und Sicherheit. Er hat einen M.S. und Ph.D. in Informatik von der University of North Carolina, Chapel Hill.

Hussam Mousa ist Software Engineer am Intel System Optimization Technology Center (SOTC). Sein Fokus liegt auf der Analyse der Virtualisierungsleistung, speziell die I/O-Leistung für Anwendungen der Enterprise-Klasse. Er hat bei akademischen Tagungen verschiedene Papiere zum Thema Analyse der Virtualisierungsleistung veröffentlicht. Er machte 2010 seinen PhD an der University of California, Santa Barbara, und 2007 seinen B.S. an der American University in Kairo. Er arbeitet seit 2007 bei Intel.

Karthik Narayanan ist Software Engineer bei Intel und arbeitet an Enterprise- und Management-Anwendungen, Clustering sowie High-Availability On-Demand-Computing, sowohl nativ als auch virtualisiert. Vor seinen mittlerweile über 4 Jahren bei Intel sammelte er Erfahrung bei Softwarefirmen in New York und Indien. Er hat einen Bachelor in Ingenieurswissenschaften von der Madras University in Indien und einen M.S. in Informatik von der University of Toledo, USA.