Intel® Developer Zone:
Intel® Software Academic Program

The Intel® Software Academic Program provides Intel® Software Development Products to faculty teaching parallelism and other advanced technologies. We want to work with you to ensure the next generation of computer scientists, software engineers can develop software that maximizes performance on today's and tomorrow's hardware

Software Development Tools
Our tools suites include industry-leading C, C++ and FORTRAN compilers; performance and parallel libraries; error checking, performance profiling and cluster analyzers. Apply for a grant of a one-year, renewable software tools license for classrooms through your IDZ membership account at no cost.

Course Ware
A wide variety of classroom materials are available for download and use on the Intel® Developer Zone Academic Courseware page. You do not need to be a member of the Intel® Developer Zone to download and use these course materials.

Want to explore more? The Intel® Developer Zone has a wide variety of technical forums to get answers to both your hardware and software questions.

Intel® Parallel Computing Centers

Intel® Parallel Computing Centers are universities, institutions, and labs that are leaders in their field. The centers are focusing on modernizing applications to increase parallelism and scalability through optimizations that leverage cores, caches, threads, and vector capabilities of microprocessors and coprocessors. By enabling the advancement of parallelism, the Intel® Parallel Computing Centers will accelerate discovery in the fields of energy, finance, manufacturing, life sciences, weather, and beyond.

The participating institutions so far:

Read more

Events Update

SSG Brazil sponsored the 25th edition of International Symposium on Computer Architecture and High Performance Computing. An Industrial track was delivered, introducing the Intel Xeon Phi architecture and Software tools. Intel also supported a Software Marathon parallel programming challenge

Missed the Super Computing conference? Hear all about Program Director Michael Smith’s highlights presentation, as well as his address during the Broadening Engagement in Computing Workshop.

Events Photos: SC2013

Arizona State University Student Cluster Competition:

Michael Smith and Damian Rouson, Broadening Engagement Program:

Michael Smith:

Michael Smith, Notre Dame University: Slippery Rock University: Vetria Byrd, Clemson University:


The ever increasing capabilities provided by smartphones, tablets, Ultrabooks™, and notebooks makes power efficiency more critical so that battery life keeps up with on-the-go use. Energy efficient software enables devices to support more exciting usages available when we need them. To read more about Energy Efficient Programming, click here.

The EEP tool for Faculty

This tool is for faculty and educators who want to understand the energy consumption and performance qualities of their programs and applications. Use the Intel® Software Tester Suite to understand key energy use concepts and experiment with some sample code. The Intel® Software Tester Suite consists of the Intel® Energy Efficient Performance Tester and a customized API that your application can use to expose performance metrics.
Click here to access the Intel® Energy Efficient Performance Guide.
Click here to download the Intel® Software Tester Suite.

Intel Software Development Assistant - Measure Energy Consumed & Performance

The Intel® Software Development Assistant (ISDA) is a software suite that provides important application profiling and testing software for ISVs and the applications they develop. The current release of ISDA offers the Energy Efficient Performance (EEP) module, which you can use to take energy measurements from the system as it executes specific workloads within your application or as it executes your application as a whole. Download Here.

Featured Member

Benoit Pradelle and members of the energy team in the PerfCloud project at the University of Versailles, France
recently published the paper, Evaluation of CPU Frequency Transition, with support from the Intel EEP tools. Their work begin in July 2012, with partners at the Exascale Laboratory at Versailles, a join lab between Intel, CEA, GENCI, and the University of Versailles.

To read more, download the full paper here ›
Read Academic Tech Briefs

The Intel Software Academic Program announces new software projects for security coursework, labs and experiments. These tools support the Intel Security Curriculum Series and can be used in general aspects of security instruction. Below are our first projects on the Advanced Encryption Standard (AES), Trusted Boot, Identity Protection and Digital Random Number Generator (DRNG). Please check back for more education material on security.

Security Course Projects

Advanced Encryption Standard (AES) Crypto Performance Analysis Project (18 MB requires environment setup)- This experiment compares a high performance software implementation of AES with that of the AES-New Instruction optimized Intel AES sample library.

TXT/Trusted Boot (TXT/TB) Project - Use TXT Tboot to set up an attestation server to attest a client with TPM.

Identity Protection Technology (IPT) Project - Use One Time Password (OTP) to access a website configured to use OTP authentication. Measure the performance of Intel OTP.

Digital Random Number Generator (DRNG) Analysis Project - This experiment analyzes and compares the statistical properties of Intel DRNG/RDRAND with software RNG implementations.

Featured Member


The Intel seed-board program recently donated BIS-6630 Norco development kits to Professor Patrick Schaumont, currently an Associate Professor at the Bradley Department of Electrical and Computer Engineering, Virginia Tech. As part of the Handheld Computer Security course in Spring 2013, Schaumont designed a semester wide class project to investigate vector processing techniques to accelerate modular multiplications in prime fields using the SSE2 instruction-set extensions in Intel’s Atom CPU.


To read more, download the full paper here
Read Academic Tech Briefs

Exciting new capabilities have been added to our flagship software development products, Intel® Parallel Studio XE and Intel® Cluster Studio XE. Learn more.

C++ and Fortran Compilers

Libraries and Parallel Models

Analysis Tools


The Intel Software Academic Program provides Intel® Software Development Products to faculty teaching parallelism and other advanced technologies. We want to work with you to ensure the next generation of computer scientists, software engineers can develop software that maximizes performance on today's and tomorrow's hardware. Our tools suites include industry-leading C, C++ and Fortran compilers; performance and parallel libraries; error checking, performance profiling and cluster analyzers.

You may apply for a grant of a one-year, renewable software tools license for classrooms.

Request License

Additional Resources

Software Tools – Check out a comprehensive tool suite that includes an initiative threading assistant, optimizing compiler, libraries and much more.

Featured School

Mexico's top-ranked private university Tecnológico de Monterrey (Tech de Monterrey), is the latest recipient of an Intel® Xeon Phi™ lab. The flagship campus is in the city of Monterrey, a strategic place for the academic, economic and industrial development of Mexico. The Intel Xeon-Phi Remote Testing Lab will be used by 2,000 current IT students at the campus in Monterrey and it will also support academic activities for students from other campuses and other universities across Mexico, particularly those with large IT programs. Tech de Monterrey plans to host the Xeon-Phi remote testing access lab to demonstrate software scaling and conduct research supporting parallelism.

Access the Courseware Library

Find lectures, demos and other material created by university professors and Intel experts in Parallel Programming, Security, Embedded Systems and more. Use these materials to teach workshops, new courses or to supplement existing courses. Please share your feedback after downloading course material.

Content for Mobile Computing Courseware is now available. This includes education resources and course curriculum from subject matter experts and faculty worldwide.

Remote access to the Intel Manycore Testing Lab is an additional resource to enhance your students’ learning experience

Featured Course: Intro to Parallel Programming


Module 1:
Why Parallel, Why Now

Module 2:
Problem Decompositions

Module 3:
Finding Parallelism

Module 4:
Shared Memory Considerations

Module 5:
OpenMP for Domain Decomposition

Module 6:
Confronting Race Conditions

Module 7:

Module 8:
OpenMP for Task Decomposition

Module 9:
Implementing Task Decomposition

Module 10:
Predicting Parallel Performance

Module 11:
Improving Parallel Performance

Module 12:
Reducing Parallel Overhead

Accompanying Lab Files


Academic Opportunities

Intel® Atom™ processors in Academia
See how you can use Intel Atom processors in the classroom.
Teach Parallel Hear from the people leading the charge to think and teach parallel.



Speculative Parallel DFA Membership Tests
By Eliana Penzner (Intel)Posted 03/31/20140
In a recent paper published in the International Journal of Parallel Programming, Yousun Ko, Minyoung Jung, Yo-Sub Han and Bernd Burgstaller presented techniques to parallelize memberships tests for Deteministic Finite Automata (DFAs). With the use of the Intel Academic Program Manycore Testing L...
Broadening Participation in Visualization Workshop
By Michael A. Smith (Intel)Posted 03/19/20140
Clemson University hosted the first Broadening Participating in Visualization workshop on February 10-11, 2014. I was honored to serve as a panelist and keynote on visualization from an industry perspective. Visualization plays a significant role in the exploration and understanding of data acros...
Intel® Software Conference (ISTEP) in Brazil
By Eliana Penzner (Intel)Posted 03/12/20140
In 2013, the Intel® Software Academic Program, working together with the Intel Software Development Tools Team, brought Intel Software Conference to São Paulo and Rio de Janeiro. The conference received 238 attendees in total, delivering hands on lab trainings and theoretical lectures. The infras...
Introducing the new Intel Student Partners - Kenya!
By Rachel GichingaPosted 02/24/20144
We’re very pleased to announce this year’s cohort of Intel Student Partners! This is an extremely talented group of university students picked from 5 universities across Kenya, who will be running Intel activities on their campuses over the course of the year. This program is designed to enable s...


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Michael Smith is the Director of the Intel Software Academic Program. He leads collaborations in high performance computing, parallel computing, security, visualization and mobile computing.
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Raghudeep Kannavara is a security architect in the Software and Services Group (SSG) at Intel Corp where he is responsible for driving security and privacy requirements and solutions for specific Intel products.
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Haidong Xia is a security designer for the Cloud Platforms Group in the Intel® Datacenter and Connected Systems Group (DCSG).
Read More

Awards for Parallelism
By Paul Steinberg (Intel)13
This Thread is to discuss our new Microgrant Awards for Parallelism Cours Materials. Intel is sponsoringcash awards to encourage the creation of teaching content, including tools, games, labs, demonstrations and other examples that can be used in the classroom to introduce parallel programming concepts into computer science, computational sciences, and other science and math courses at many levels. Find out how to gethelp to support the creation, publication, or dissemination of your course materials. Grants from USD $500-$1500 will be available through June 2011. Apply early for the best chance to get your grant.More information and entry.
Is it possible to disable or not use the Last Level Cache in Intel IvyBridge CPU?
By Mike X.0
Hi, I want to do an experiment which test the performance degradation and effect on the scheduling when CPU has no shared Last Level Cache. I was able to "disable" all caches, i.e., not allowing the OS to use the caches.  However, I have to do some experiment when CPU only has the private L1 and L2 cache, and does not use the L3 shared cache.  So my question is: Is it possible to not use the L3 cache but use the L1 and L2 cache for the IvyBridge CPU?  I looked at the Intel Developer Manual. I cannot find any text which confirm if this is possible or not.  Could anyone help me? Thanks,  
clock cycles for complex multiplication and complex addition in i5 Processor
By Jorge Lorente0
Hello, I have an Intel Core i5-3317U Processor (1.7Ghz 4GB RAM) How many clock cycles does a complex addition and a complex multiplication each take separately for my i5 processor? thanks, Jorge
I need a software for simulating Clovertown
By Hamid Reza K.0
Hi all, I am researching on CMP scheduling. I need a software to simulate Clovertown where is able to run my muli-threaded applications. The software must support cohorency protocols and its simulatio speed is high. I have tested various simulators, but some of them havenot satisfied my needs or thier simualtion speed was slow. Could you help me to find a suitable simulator? thanks
Working principle of Intel (R) Processor Diagnostic Tool
By Alexey B.0
Hi! My name is Alexey, I'm going to write a term paper on Error reaviling in processor functioning. Could you be so kind to consult me about Intel(R) Processor Diagnostic Tool. I took advantage of the proposed program to test CPU, but for the completion of this work I need to provide technical documentation and and function of software that was used.I would be very grateful, if you could help me in this matter. I was able to find almost all aspects of interest to me, except the principle of operation of the program. I know that Prime95 calculates Mersenne prime numbers and Linpaсk finds the solution of linear equations. I would be very grateful if you would have helped me find how Intel Processor Diagnostic Tool tests the processor.   Thanks, Alexey
Inconsistency in the IPCC RFP
By Raghunath R.0
The RFP page for Intel Parallel computing centers has Dec 2nd has the deadline for submitting proposals: while, the top-level academic program page has Dec 1st as the deadline: Does anyone know if the deadline was extended by a day, or if it was a typo in either one of the pages?  
how can solve fortran running error like '^K^@^@^@^A^@^@^@^@^@^@^@%^@^@^B'
By Alex Adams2
Hello profs,      I write a fortran script and compile it with intel fortran compiler. Then I run it and mostly it works so well. the functin of scripts is to read some strings from the files containing losts of lines.      but when it read one of the piles of files, error reported 'forrtl: severe (64): input conversion error, unit -5, file Internal Formatted Read'.      I checked the codes and find the issue attributed to the line ' read(string, '(f14.3)') xfloatn' (where, string set to character*16, xfloatn to real*8).      Also when I debugged the program again, I outputed the string into files and checked what happened.  I find the lines like the following:     ^K^@^@^@^A^@^@^@^@^@^@^@%^@^@^B   150382809.969 7  ^K^@^@^@^A^@^@^@^@^@^@^@%^@^@^B   150385056.018 7  ^K^@^@^@^A^@^@^@^@^@^@^@%^@^@^B     In the upper lines, only lines containing float number is valid, the other is not hoped. I never meet with this situation before. Can you help me out for this issue.     BTW, I run ...
Learning the ropes of intel processors!
By Matthew G.0
Hello! My name is Matthew Gillen, I am 13 years of age, and I am still new to processors. I have a slight basic understanding of ghz and mhz, but that is it. I am looking into getting into MicroProcessor engineering. I would love to talk to someone and learn more, if so please leave some info on how i can contact you. Thank you for reading!


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Caches in Clovertown are inclusive or exclusive?
By Hamid Reza K.0
Hello, I am researching on multi-core scheduling algorithms, and need some information about Intel Xeon 5310 (Clovertown) processor. As you know, Clovertown is a two-package quad-core processor. Each package consists of a dual core processor. So, Could you tell me caches are inclusion or exclusion in Clovertwon? I asked the question from Intel support centre, and found that all caches are inclusive. So, I have another question. Suppose block x is loaded to L1 cache of core0 in Clovertown (block x will be loaded to shared L2 cache). Then, the block is evicted from L1 of core0. (Therefore, block x will be evicted form shared L2). After a while, core1 accesses to block x. In this case, L2 cannot help core1 to retrieve block x. In the other words, inclusion has negative effect on thread affinity. Isn't it true?   Thanks
The MTL is temporally down for renovations and relocation
By Mike Pearce (Intel)1
The Manycore Testing Lab (MTL) is closed for renovations and relocation and will reopen in late October. We apologize for any inconvenience during this closure.   
VTune driver and hardware event
By Samuel S.2
Hi all, I am trying to run an analysis using event-based sampling with VTune Amplifier XE from the command line. The documentation says it is done with:    amplxe-cl -collect-with runsa -knob event-config=<list of events> But I don't know what the hardware events supported by the CPUs on MTL are. Is it the 32nm Intel(R) Xeon(R) Processor, as listed on, under Reference for Processor Events? Even if I launch amplxe-cl to record, say, INST_RETIRED.ANY events, it gives me the error:     Error: VTune Amplifier XE sampling driver is inaccessible. Make sure the driver is installed and you have permissions to access it. I have seen that VTune Performance Analyzer 9.1 is installed on /opt/intel/vtune. Is it supported on MTL? This version should list the events with:     vtl query -c sampling but, as a normal user, I can't start the vdk driver with insmod-vtune. Thank you fo...
Error: A license for CCompL could not be obtained
By Anne Bracy2
I am revisiting code that I wrote on the Manycore Testing Lab a few months ago and am no longer able to compile it. The error I am getting is as follows:  Error: A license for CCompL could not be obtainedYour license is not current enough to allow you to use thisnewer version of our software. Usually this occurs becauseyour support services license expired before we created thisversion. You will need to purchase a new license. License file(s) used were (in this order): < list of 21 files > Please visit to obtain license renewal information. icpc: error #10052: could not checkout FLEXlm license Any clues? Thanks, Anne
Qualification for obtaining the access to the many core testing lab
By Motiur R.0
Hi, I have applied for an access to the many core testing about a month ago . I still do not received a response from Intel . How long generally do someone has to wait for a confirmation . And whom should I mail to see whether I have the qualification to recieve an access . My semester presentation is due next month and it would be beneficial if I could have the lab facilities at hand . Thanks/
Cilkplus on MTL
By Anne Bracy4
I am trying to run a simple cilk plus program on MTL. The program runs both a serial (non-threaded) and a parallel (using cilk_spawn) version of the same code and reports the timing results for both versions. I can compile it and run it on the login node, but it shows no speedup in the parallel version because it does not have access to multiple CPUs. When I try to submit the job using qsub (hoping to get access to multiple cores), I get the following output file: ----- Warning: no access to tty (Bad file descriptor).Thus no job control in this shell.MANPATH: Undefined variable./home/knag/knag-s01/01/code/sol/stocks: error while loading shared libraries: cannot open shared object file: No such file or directory ------ The first two errors (tty & MANPATH) I'd like to fix but, but am more concerned about the third error. How can I let whatever core is running my job know where the is? I can update my LD_LIBRARY_PATH to point to the right place (addi...


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