cache-config

Set the cache hierarchy to collect modeling data for CPU cache behavior during Trip Counts & FLOP analysis.

GUI Equivalent

Project Properties > Analysis Target > Trip Counts and FLOP Analysis > Cache simulator configuration

Syntax

--cache-config=<string>

Arguments

<string> follows this template:

[num_of_level1_caches]:[num_of_ways_level1_connected]:[level1_cache_size]:[level1_cacheline_size]/

[num_of_level2_caches]:[num_of_ways_level2_connected]:[level2_cache_size]:[level2_cacheline_size]/

[num_of_level3_caches]:[num_of_ways_level3_connected]:[level3_cache_size]:[level3_cacheline_size]

For example: 4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l

Actions Modified

collect=tripcounts --enable-cache-simulation

Usage

When no specific configuration is set, the Intel Advisor uses system cache hierarchy for modeling.

Note

Cache simulation modeling applies to the following analyses:

  • Memory Access Patterns - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.

  • Trip Counts and FLOP - This enhanced simulation functionality models multiple levels of cache for a downstream GUI Roofline chart or Roofline interactive HTML report. To enable enhanced simulation functionality in a GUI Roofline chart: Set the ADVIXE-EXPERIMENTAL=int_roofline environment variable.

Example

  1. Run a Survey analysis.

  2. Run a Trip Counts & FLOP analysis. Model cache behavior for the specified configuration.

$ advixe-cl –-collect=survey –-project-dir=./advi -- myApplication
$ advixe-cl --collect=tripcounts --flop –-enable-cache-simulation --cache-config=4:8w:32k:64l/4:4w:256k:64l/1:16w:6m:64l –-project-dir=./advi -- myApplication

See Also

For more complete information about compiler optimizations, see our Optimization Notice.