DE10-Nano Board Schematic

Figure below shows the block diagram of the DE10-Nano development board. Connections are made through the Cyclone V* SoC FPGA. See attached PDF for full schematic details.

block diagram

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PDF icon de10-nano-schematic.pdf1.58 MB
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1 comment

Gisselquist, Dan's picture

This is the wrong schematic for the DE10.  Internally, it describes itself as the schematic for the DE0-Nano, not the DE10-Nano.  Further, it has the wrong chip identified within it.


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