DE10-Nano Board Schematic

Figure below shows the block diagram of the DE10-Nano development board. Connections are made through the Cyclone V* SoC FPGA. See attached PDF for full schematic details.

block diagram

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Just repeating Dan's comment above (which, 20 months later, remains unresolved).

The attachment on this page named "de10-nano-schematic.pdf" is a misnamed schematic for the DE0-Nano instead.

If anyone else is looking for the correct DE10-Nano schematic, I found the correct "de10-nano.pdf" in the "Schematic" folder on the CD-ROM image downloadable from the DE10-Nano resources page: http://de10-nano.terasic.com/cd

Hopefully Intel will eventuially upfdate this page with the correct DE10-Nano schematic PDF.

This is the wrong schematic for the DE10.  Internally, it describes itself as the schematic for the DE0-Nano, not the DE10-Nano.  Further, it has the wrong chip identified within it.

Dan

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