DE10-Nano Board Schematic Published on February 3, 2017 Translating...TranslateChinese SimplifiedChinese TraditionalEnglishFrenchGermanItalianPortugueseRussianSpanishTurkishThis is a computer translation of the original content. It is provided for general information only and should not be relied upon as complete or accurate.Sorry, we can't translate this content right now, please try again later. Figure below shows the block diagram of the DE10-Nano development board. Connections are made through the Cyclone V* SoC FPGA. See attached PDF for full schematic details.Download Learn More Related AttachmentSize de10-nano-schematic.pdf1.58 MB For more complete information about compiler optimizations, see our Optimization Notice.