Intel® C++ Compiler 18.0 for Windows* Release Notes for Intel® Parallel Studio XE 2018

Intel® C++ Compiler 18.0  for Windows* Release Notes for Intel® Parallel Studio XE 2018

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 18.0

Change History

Changes since Intel® C++ Compiler 17.0 (New in Intel® C++ Compiler 18.0)

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System Requirements

  • A PC based on an Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions (Intel® 2nd Generation or newer Generation of Intel® Core™ i3, i5, or i7 processors and Intel® Xeon® E3 or E5 processor family, or compatible non-Intel processor)
  • 2GB of RAM (4GB recommended)
  • 4GB free disk space for all features
  • For Intel® MIC Architecture development/testing:
  • For offload to or native support for Intel® Graphics Technology development/testing
    • The following processor models are supported: 
      • Intel® Xeon® Processor E3-1285 v3 and E3-1285L v3 (Intel® C226 Chipset) with Intel® HD Graphics P4700 
      • 5th Generation Intel® Core™ Processors with Intel® Iris™ Pro Graphics, Intel® HD Graphics
      • 4th Generation Intel® Core™ Processors with Intel® Iris™ Pro Graphics, Intel® Iris™ Graphics or Intel® HD Graphics 4200+ Series 
      • Please note: Intel® Xeon® processors are only supported with the chipsets listed. Intel® Xeon® configurations with other chipsets are not supported. Previous generations of Intel® Core™ processors are not supported. Intel® Celeron and Intel® Atom™ processors are also not compatible.
    • The latest 32-bit or 64-bit graphics driver with support for Intel® Graphics Technology (available at the Download Center)
    • A version of binutils (specifically 2.24.51.20131210) for Windows (available at http://intel.ly/1fHX7xO)
      • Note that after installing binutils, you will need to set your PATH to include the directory containing ld.exe.
  • Microsoft Windows 7* (SP1), Microsoft Windows 8*, Microsoft Windows 8.1*, Microsoft Windows 10*, or Microsoft Windows Server 2012 (R2)* (embedded editions not supported) , Windows Server 2016*[1]
    • On Microsoft Windows 8, Microsoft Windows 8.1, and Microsoft Windows Server 2012, the product installs into the "Desktop" environment. Development of "Windows 8 UI" applications is not supported. [2]
  • To use the Microsoft Visual Studio development environment or command-line tools to build IA-32 or Intel® 64 architecture applications, one of:
    • Microsoft Visual Studio 2017* Professional Edition (or higher edition) with 'Desktop development with C++' component installed
    • Microsoft Visual Studio 2015* Professional Edition (or higher edition) with 'Common Tools for Visual C++ 2015' component installed [3]
    • Microsoft Visual Studio Community 2015* with 'Common Tools for Visual C++ 2015' component installed [3]
    • Microsoft Visual Studio 2013* Professional Edition (or higher edition) with C++ component installed
    • Microsoft Visual Studio Community 2013* with C++ component installed
  • To use command-line tools only to build IA-32[1] architecture applications, one of:
    • Microsoft Visual C++ Express 2015 for Windows Desktop*
    • Microsoft Visual C++ Express 2013 for Windows Desktop*
  • To use command-line tools only to build Intel® 64 architecture applications, one of:
    • Microsoft Visual C++ Express 2015 for Windows Desktop*
    • Microsoft Visual C++ Express 2013 for Windows Desktop*
    • Microsoft Windows* Software Development Kit for Windows 8*
  • To read the on-disk documentation, Adobe Reader* 7.0 or later

Notes

  1. Applications can be run on the same Windows versions as specified above for development. Applications may also run on non-embedded 32-bit versions of Microsoft Windows earlier than Windows XP, though Intel does not test these for compatibility.  Your application may depend on a Win32 API routine not present in older versions of Windows.  You are responsible for testing application compatibility. You may need to copy certain run-time DLLs onto the target system to run your application.
  2. The Intel® C++ Compiler does not support development of Windows 8* UI apps.  We are always interested in your comments and suggestions.  For example, if you want to use the Intel® C++ Compiler or other Intel software development capabilities in Windows 8 UI apps, please file a request at the Intel® Online Service Center.
  3. To use the Intel® C++ Compiler with Microsoft Visual Studio 2015*, it is necessary to install the 'Common Tools for Visual C++ 2015' component from Visual Studio.  This article explains how.
  4. This article explains how to use the Intel® C++ Compiler with Microsoft Visual Studio 2017*, 
  5. Intel continually evaluates the markets for our products in order to provide the best possible solutions to our customer’s challenges. As part of this on-going evaluation process Intel has decided to not offer Intel® Xeon Phi™ 7200 Coprocessor (codenamed Knights Landing Coprocessor) products to the market
    • Given the rapid adoption of Intel® Xeon Phi™ 7200 processors, Intel has decided to not deploy the Knights Landing Coprocessor to the general market.
    • Intel® Xeon Phi™ Processors remain a key element of our solution portfolio for providing customers the most compelling and competitive solutions possible.

Intel® Manycore Platform Software Stack (Intel® MPSS)

The Intel® Manycore Platform Software Stack (Intel® MPSS) may be installed before or after installing the Intel® C++ Compiler.
Using the latest version of Intel® MPSS available is recommended. It is available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com as part of your Intel® Parallel Studio XE for Windows* registration.
Refer to the Intel® MPSS documentation for the necessary steps to install the user space and kernel drivers. 

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How to use the Intel® C++ Compiler

Intel® Parallel Studio XE 2018: Getting started with the Intel® C++ Compiler 18.0 for Windows* at <install-dir>\documentation_2018\en\compiler_c\ps2018\get_started_wc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Microsoft Visual Studio*.

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Documentation

Product documentation is linked from <install-dir>\documentation_2018\en\compiler_c\ps2018\get_started_wc.htm.

Online Help format in Microsoft Visual Studio*

New help menu items to link to online getting started documents.
Context sensitive help on F1 is not available

Offline Core Documentation Removed from the Installed Image

Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.

  • When Set Help Preference is set to Launch in Browser and you hit F1 in Tools>Options>F# Tools or Tools>Options>Intellitrace, the browser appears twice.
  • Chrome*: When arriving at a topic from Search or Index, the Table of Contents (TOC) does not sync, nor does the Sync TOC link work. 
  • Firefox*: The TOC loses context easily. Search is case sensitive.
  • Safari*: Response on Windows* is slow.

Japanese Language Support

Japanese language support is not provided with this release of the product.

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Intel-provided debug solutions

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Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials

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Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

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New and Changed Features

The following features are new or significantly enhanced in this version.  For more information on these features, please refer to the documentation.

Microsoft Visual Studio 2017* Support

Integration support for Intel® C++ compiler added for Microsoft Visual Studio 2017*. Refer to System Requirements for additional information.

monotonic and overlap keywords for ordered block in simd context

New keywords for existing #pragma omp ordered simd

  • #pragma omp ordered simd monotonic()
  • #pragma omp ordered simd overlap(expr)
  • #pragma omp simd reduction(=: list)

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

New /qopt-zmm-usage option

You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.

Support of hardware based PGO

Profile Guided Optimization (PGO) Hardware-based event sampling is a new low overhead model to get (many) benefits of PGO using the Intel® Compiler and the Intel® VTune™ Amplifier. Data collection works on systems where Intel® VTune™ Amplifier is supported.

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

For more information about Parallel STL, see Getting Started and Release Notes .

Change in behavior of extract ( _mm256_extract_epi8 ) instrinics return type

Intel defined 256-bit vector intrinsics _m256_extract_epi8/epi16(__m256i a, const int index) return int instead of __int8/__int16 values.

New option /Qimf-use-svml to enforce SVML

New option forces use of SVML where currently LIBM is used, for scalar math. This guarantees bitwise-same result of computations made with vectorized code vs computations made with scalar code. With this feature the compiler vectorizes math functions in /fp:precise FP model and vectorized code produces results consistent with scalar code results. 

CET - Control-Flow Enforcement Technology support

Control-flow Enforcement Technology (CET) defends a program from certain attacks that exploit vulnerabilities, e.g. Return-oriented Programming (ROP) and similarly Call/Jmp-oriented Programming (COP/JOP). Please refer to the preview document for more details.

New compiler option /Qcf-potection[:keyword] introduced in the compiler to support CET.

Compile time dispatching for SVML calls

The compiler default behaviour is changed for SVML functions and a call to cpu-specific SVML entry is performed. Specifying new option /Qimf-force-dynamic-target reverts to the previous behavior and dynamic SVML dispatching is used.

Features from OpenMP* TR4 Version 5.0 Preview 1

Language features for task reductions from the OpenMP* Technical Report 4 : Version 5.0 Preview 1 specifications are now supported.

  • TASKGROUP now has the TASK_REDUCTION clause.
  • TASK includes now has the IN_REDUCTION clause
  • TASKLOOP now has the REDUCTION and IN_REDUCTION clauses

For more information, see the compiler documentation or the link to the OpenMP* Specification above.

Support for more new features from OpenMP* 4.0 or later

  • taskloop construct feature #pragma omp taskloop[clause[[,]clause]..]
  • Support for #pragma omp for linear (list [ : linear-step ])
    •  where list is either list or modifier(list)
  • Support for ref, val, and uval modifiersfor the linear clause
    •  Examples:  linear(ref(p)), linear(val(i):1), linear(uval(j):1)
  • Support for #pragma omp simd simdlen(n)
  • Support for #pragma omp ordered [simd]
  • Reductions over whole arrays:  int x[n]; #pragma omp simd reduction(+:x)
  • Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)
  • support for clauses SIMD and NONMONOTONIC modifiers for #pragma omp for schedule :
    • The Intel® C++ Compiler 18.0 include SIMD and NONMONOTONICmodifiers extenstion to schedule clause to enhance user control of how interations of the for loop are divided among threads of team. See the Intel® C++ Compiler User’s Guide for more details.
  • support for array sections as list items in the reduction clause
    • reduction(reduction-identifier:list) If a list item is an array section, it is treated as if reduction clause is applied to each seperate element of the section. The elements of the private array sections will be allocated contiguously

C++17 features supported

The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:

  • Static assert with no message (N3928)
  • Relaxed Range based for loops (N3994)
  • Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

C11 features supported

The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:

  • Support for all C11 features including C11 keyword _Atomic and __attribute((atomic))
  • Please see C11 Support in Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

  • All –o* options replaced by –qo* options

    All the –o* options deprecated in the previous release have been replaced with –qo* options in this release with one noted exception, there is no change to the –o option for Linux* and macOS* used to name the output file.

    On Windows*, this change impacts compiler options passed to the target compilation with the /Qoffload-option Compiler option.

    A new diagnostic is issued when any now replaced –o option is used. For example:

    $ icc -openmp example.c
    icc: command line error: option '-openmp' is not supported. Please use the replacement option '-qopenmp'

    Options affected:

    -[no-]openmp
    -openmp-lib=<arg>
    -openmp-link=<arg>
    -[no-]openmp-offload
    -[no-]openmp-simd
    -openmp-stubs
    -openmp-threadprivate=<arg>
    -openmp-report[=<level>]
    -openmp-task=<arg>
    -opt-args-in-regs=<arg>
    -[no-]opt-assume-safe-padding
    -opt-block-factor=<arg>
    -[no-]opt-calloc
    -[no-]opt-class-analysis
    -[no-]opt-dynamic-align
    -[no-]opt-gather-scatter-unroll
    -[no-]opt-jump-tables=<arg>
    -opt-malloc-options=<arg>
    -[no-]opt-matmul
    -[no-]opt-mem-layout-trans=<arg>
    -[no-]opt-multi-version-aggressive
    -[no-]opt-prefetch[=<val>]
    -opt-prefetch-distance=<arg>
    -opt-ra-region-strategy[=<arg>]
    -[no-]opt-report-embed
    -opt-report-file=<arg>
    -opt-report-filter=<arg>
    -opt-report-format=<arg>
    -opt-report-phase=<arg>
    -opt-report-routine=<arg>
    /opt-report-help
    /opt-report[=<arg>]
    /opt-report-per-object
    /opt-streaming-cache-evict=<arg>
    /opt-streaming-stores=<arg>
    /[no-]opt-subscript-in-range
    /opt-threads-per-core=<arg>

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

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Support Deprecated

Intel® Cilk™ Plus deprecated in 18.0

Intel® Cilk™ Plus is a deprecated feature in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus

Support for 32-bit icc wrapper deprecated in 18.0

icl: remark #10421: The IA-32 target wrapper binary 'icl' is deprecated. Please use the compiler startup scripts or the proper Intel(R) 64 compiler binary with the '-Qm32' option to target the intended architecture

 

Support Removed

Support for Microsoft Visual Studio 2012* has been removed in 18.0

Support for the Intel® Xeon Phi™ x100 product family coprocessor (formerly code name Knights Corner) is removed in this release

  • In Visual Studio, code Generation [Intel C++] >Offload Target Architecture(/Qoffload-Arch): "mic" argument is de-exposed
  • "mic" value saved in project for Intel C++ Compiler 17.0 platform toolset is updated to "default" value after upgrading to 18.0 platform toolset

Support for installation on IA-32 hosts has been removed

Support for installation on IA-32 hosts has been removed.  Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option /Qm32

_GFX_enqueue  has been removed

_GFX_enqueue has been removed and should be replaced with _GFX_offload 

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Known Limitations

Offload Applications Targeting the Intel® Xeon Phi™ Coprocessor Requires Microsoft Visual Studio 2015* or 2017

Due to a limitation with the Intel® Manycore Platform Software Stack (Intel® MPSS) supporting the Intel® Xeon Phi™ coprocessor x200 product family, Microsoft Visual Studio 2013* is not currently usable for execution of offload applications. While you can build offload applications with Microsoft Visual Studio 2013*, the execution fails with the error: "The remote process indicated that the following libraries could not be loaded libioffload_target.so.5 libiomp5.so libcilkrts.so.5 offload error: cannot start process on the device 0 (error code 19)" Running the offload application built under Microsoft Visual Studio 2013* requires using either Microsoft Visual Studio 2015* or 2017 run as ‘devenv’ from a "Compiler 18.0 Beta for Intel 64 Visual Studio 2015/2017” command-prompt window. However, This error message is only for vs2015/2017 run from shortcut, not from cmd with PSXE environment. VS2013 fails with another issue and messages.The recommended work around is to use either Microsoft Visual Studio 2015* or 2017 exclusively for building and running Offload applications targeting the Intel® Xeon Phi™ coprocessor. This limitation may be addressed in a future the Intel® Manycore Platform Software Stack (Intel® MPSS).

Pointer Checker requires a dynamic runtime library

When using the /Qcheck-pointers option, the runtime library libchkp.dll must be linked in. When using options like /MD with /Qcheck-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at http://intel.ly/1jV0eWD for more information.

Intel® Compiler Help Documentation fails to launch from IDE when installed on Japanese version of Windows*

Some multi-pane documents do not display correctly in the Visual Studio* internal browser

There is a limitation of Visual Studio* internal browser that some multi-pane documents do not display correctly, the table of contents appears in the left pane, but the right pane does not display any content.
Workaround: Access the same documentation from the Visual Studio Help menu.

Mixed Microsoft* / Intel compilation of 256 vector bit type parameters may generate code that causes an access violation at runtime

A general protection fault caused by an unaligned data access may occur when an application is built using two different compilers - the Microsoft Visual C++ 2013* compiler and the Intel® C++ Compiler 15.0 or above. The problem may arise when 256 vector bit type parameters are passed by reference in a call, when the caller is built with Visual C++*, and the parameters are accessed by functions built with the Intel C++ Compiler.

The problem arises due to a mismatch in the alignment of the 256 vector bit type parameters. 

This problem will not occur when the /Qx<code> compiler option is used with <code> equal to AVX or with a newer code value, such as CORE-AVX-I, CORE-AVX2, etc., due to the fact that unaligned access instructions are used in these instances unless  __mm256_stream_*  (non-temporal data load/store intrinsics)  are used explicitly in the application source code.  

Visual Studio Known Issues

    • Intel® C++ compiler integration to Visual Studio 2017* issues

      There are different integration issues observed with Microsoft* Visual Studio 2017. Problems are intermittent and not reproducible on every system. We haven't seen integration issues with latest Visual Studio 2017 version 15.3.3. Please refer to https://software.intel.com/en-us/articles/intel-software-development-tools-integration-to-vs2017-issue for details.

    • MSVCP90D.dll (or other Microsoft runtime DLL) is missing

      There are situations where the sample projects provided (or any Microsoft Visual C++* project potentially) could run into a runtime System Error where the application cannot find a Microsoft Visual Studio* runtime DLL.  This is related to manifest files and SXS assemblies potentially missing.  The simplest solution is to go to your redist directory for the version of Microsoft Visual Studio* you are using (default location would be c:\program files[ (x86)]\Microsoft Visual Studio X.X\VC\redist).  There will be several subdirectories under this location, sorting files out by amd64, x86 or Debug_NonRedist (if you have D in the runtime name, this usually indicates a Debug library found in this folder).  Find the appropriate folder that contains the runtime you are looking for, and then copy the entire contents of that folder (including a .manifest file) to the directory where the .exe you are trying to run is located.
    • Warning #31001:The dll for reading and writing the pdb (for example, mspdb110.dll) could not be found on your path.

      When using Microsoft Visual Studio Express*, compilation for IA-32 with -debug (General > Debug Information Format) enabled may result the warning: warning #31001: The dll for reading and writing the pdb (for example, mspdb110.dll) could not be found on your path. This is usually a configuration error. Compilation will continue using /Z7 instead of /Zi, but expect a similar error when you link your program. The warning is expected and occurs because a 64 bit Windows* applications (i.e. the Intel® Fortran compiler) must use 64 bit dlls (https://msdn.microsoft.com/en-us/library/windows/desktop/aa384231(v=vs.85).aspx); however, Microsoft Visual Studio Express* only provides a 32 bit version of mspdb*.dll. The missing 64 bit version leads to the warning. This is a warning-level diagnostic that does not impede successfully building an executable; however, debug information requested is embedded into the object (.obj) file for use with the debugger. No .pdb file is produced by the compiler when /Z7 is enabled.
    • Intel® C++ and Fortran compilers integration into Visual Studio 2017 for PSXE 2018 Beta.
      • Base platform toolset functionality is limited in VS2017. Available base platform toolsets are v141 and v141_xp. If you want to use older build environment like v140, v140_xp, v120, v120_xp, install Intel® C++ compiler integration into corresponding version of Visual Studio and build project from it or use Base platform toolset functionality from older supported versions of Visual Studio.
      • Files generated by Intel® Fortran Module Wizard are not added to the Fortran project automatically in VS2017. You need to add it manually - click Project-> Add Existing Item and specify location where the file was generated.
      • To compile offload application with Intel C++ and TBB support in VS2017 you need to manually pass /Qtbb option in Project Properties->C/C++->Command Line ->Additional Options.

    Known Issues with Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

    • Runtime Type Information (RTTI) not supported

      Runtime Type Information (RTTI) is not supported under the Virtual-Shared memory programming method; specifically, use of dynamic_cast<> and typeid() is not supported.
       

    Known issues for offload to Intel® Graphics Technology

    • gfx_linker: : error : command 'ld.exe' exited with non-zero exit code -107374170

      When offloading code to Intel® Graphics Technology in an x64 project, you may get a linker error with the ld.exe provided by binutils. To resolve this problem, add the binutils bin directory for the 64-bit linker to your PATH environment variable and then restart Microsoft Visual Studio*.
    • Host-side execution of offload code is not parallelized

      The compiler will generate both a target and host version of the parallel loop under #pragma offload. The host version is executed when the offload cannot be performed (usually when the target system does not have a unit with Intel® Graphics Technology enabled).The parallel loop must be specified using the parallel syntax of cilk_for or an Array Notation statement, which has parallel semantics for offload. The target version of the loop will be parallelized for target execution, but there is a current limitation where the host-side back-up version of the parallel loop will not be parallelized. Please be aware this can affect the performance of the back-up code execution significantly when offload execution does not happen in the case of cilk_for use. Array notation does not currently generate parallel code on the host, so performance should not differ here in that case. This is a known issue that may be resolved in a future product release.
       
    • Other known limitations with offload to Intel® Graphics Technology
      • On Windows 7*, for offloading to happen, the display cannot be locked. An active display is required.
      • In the offloaded code, the following are not allowed:
        • Exception handling
        • RTTI
        • longjmp/setjmp
        • VLA
        • Variable parameter lists
        • Virtual functions, function pointers, or other indirect calls or jumps
        • Shared virtual memory
        • Data structures containing pointers, such as arrays or structs
        • Globals with pointer or reference type
        • OpenMP*
        • cilk_spawn or cilk_sync
        • Intel® Cilk™ Plus reducers
        • ANSI C runtime library calls (with the exception of SVML, math.h, and mathimf.h calls and a few others)
      • 64-bit float and integer operations are inefficient

    Viewing Intel Compiler Documentation in Microsoft Edge* browser on Japanese Windows 10 OS

    • There is an issue when viewing the Intel Compiler Documentation in Microsoft Edge* browser on Japanese Windows 10 OS. The upper left corner [Content][Index][Search] buttons does not work. When clicking on it, it results in blank screen.

    • This issue is being investigated. Please use Internet Explorer to view the Intel Compiler Documentation. To set the default browser to Internet Explorer, google search "how to make Internet Explorer default browser on Windows 10".

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    Disclaimer and Legal Information

    Optimization Notice

    Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

    Notice revision #20110804

    INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

    Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

    The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

    Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

    Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to:  http://www.intel.com/design/literature.htm 

    Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: 

    http://www.intel.com/products/processor%5Fnumber/

    The Intel® C++ Compiler is provided under Intel's End User License Agreement (EULA). 

    Please consult the licenses included in the distribution for details.

    Intel, Intel logo, Pentium, Core, Atom, Iris, Intel® Xeon®, Intel® Xeon Phi™, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

    * Other names and brands may be claimed as the property of others.

    Copyright © 2017 Intel Corporation. All Rights Reserved.

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    For more complete information about compiler optimizations, see our Optimization Notice.
    For more complete information about compiler optimizations, see our Optimization Notice.