Intel® C++ Compiler 19.0 for Linux* Release Notes for Intel® Parallel Studio XE 2019

Intel C++ Compiler 19.0 for Linux* Release Notes for Intel Parallel Studio XE 2019

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation. 

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 19.0 .

Change History

Changes since Intel® C++ Compiler 19.0.3
(New in Intel® C++ Compiler 19.0.4 Eng/Jpn build 243)
IRC post date 05/23/2019

This is the final release of 2019 Update 4.  Use this compiler unless you need to validate against the same compiler used to publish SPEC (see Update 4 SPEC227 below).

  • Includes certain functional and security updates.  We recommend updating for these functional and security updates.
  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.0.3
(New in Intel® C++ Compiler 19.0.4 SPEC227 build 227)
IRC post date 05/06/2019

This is the initial release of 2019 Update 4.  This was released in Linux* and Windows* packages only (no macOS* release).
This compiler is only available in the Intel® Registration Center in packages for:

  1. Intel® Parallel Studio XE Composer Edition for Fortran and C++  Linux, 2019 Update 4 SPEC227
  2. Intel® Parallel Studio Composer Edition for Fortran and C++ Windows, 2019 Update 4 SPEC228

This version was used to publish SPEC benchmarks and to provide initial support for VS2019 Integrations and includes certain functional and security updates. We recommend updating for these functional and security updates. Use this version of the 2019 Update 4 if you are validating with the SPEC published compiler.  Otherwise the default version "Update 4 Eng/Jpn" build should be used as it is the latest Update 4 compiler (see above).  If you are macOS* user there was no SPEC compiler release (see Update 4 Eng/Jpn above).

IRC LINKS: Download the "Update 4 SPEC" compilers with the links below:

These packages contain both the Intel® C++ Compiler and the Intel® Fortran Compiler.  During installation you can select one or both compilers using the CUSTOM installation options.

For your next steps, use this table and the notes that follow the table:

Decision matrix for obtaining 2019U4 SPEC compilers

  1. If you are a licensed user of Intel Parallel® Studio XE Composer Edition for Fortran and C++ (Linux* or Windows*) you can find the SPEC compiler in your Downloads in Intel® Registration Center.  It is not the default for Update 4.  Use the Prior versions pull-down selector to find this "Update 4 SPEC" release.
  2. If you are a licensed user of CLUSTER Edition or PROFESSIONAL Edition you will not see the download for this package in your IRC Products downloads list.  Use the IRC LINKS above to directly download the package for your OS.  Your existing license for CLUSTER Edition or PROFESSIONAL Edition will work with the SPEC packages and compilers.
  3. Licensed users of the Composer Edition for Fortran or the Composer Edition for C++ use the IRC LINKS above to directly download the package for your OS.  You will also need a new license which we will provide for the combined C++ and Fortran product Intel® Parallel Studio XE Composer Edition for Fortran and C++ (for your OS) - visit Technical Support and request your license.  Make sure to indicate Linux* or Windows* or both.  Again, this does not apply to macOS*. 

Changes in this version:

  • Includes certain functional and security updates.  We recommend updating for these functional and security updates.
  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.0.2 (New in Intel® C++ Compiler 19.0.3)

  • Corrections to reported problems

Changes since Intel® C++ Compiler 19.0.1 (New in Intel® C++ Compiler 19.0.2)

  • Intel® C++ Compiler 19.0 Update 2 includes functional and security updates. Users should update to the latest version.

Changes since Intel® C++ Compiler 19.0 (New in Intel® C++ Compiler 19.0.1)

Changes since Intel® C++ Compiler 18.0 (New in Intel® C++ Compiler 19.0)

Back to top

System Requirements

  • 2GB of RAM (4GB recommended)
  • 7.5GB free disk space for all features
  • One of the following Linux distributions (this is the list of distributions tested by Intel; other distributions may or may not work and are not recommended - please refer to Technical Support if you have questions):
    • Debian* 8.0, 9.0
    • Fedora* 27,28
    • Red Hat Enterprise Linux* 6, 7
    • SUSE LINUX Enterprise Server* 12 (SP5), 15
    • Ubuntu* 18.04 LTS, 17.10
    • CentOS 7.1, 7.2
    • Intel® Cluster Ready
  • Linux Developer tools component installed, including gcc, g++ and related tools
    • gcc versions 4.3 - 8.x supported
    • binutils versions 2.20-2.29 supported
  • Library libunwind.so is required in order to use the -traceback option.  Some Linux distributions may require that it be obtained and installed separately.

Additional requirements to use the integration into the Eclipse* development environment

  • Eclipse Platform version 4.7 with:
    • Eclipse C/C++ Development Tools (CDT) 9.2.x
    • Java* Runtime Environment (JRE) 8.0 (also called 1.8) or later
  • Eclipse Platform version 4.8 with:
    • Eclipse C/C++ Development Tools (CDT) 9.3.x
    • Java* Runtime Environment (JRE) 7.0 (also called 1.8) or later

Notes

  • The Intel compilers are tested with a number of different Linux distributions, with different versions of gcc. Some Linux distributions may contain header files different from those we have tested, which may cause problems. The version of glibc you use must be consistent with the version of gcc in use. For best results, use only the gcc versions as supplied with distributions listed above. 
  • Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3, -ipo and -openmp, may require substantially larger amounts of RAM.
  • Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.

Back to top

How to use the Intel® C++ Compiler

Parallel Studio XE 2019: Getting Started with the Intel® C++  Compiler 19.0 for Linux* at <install-dir>/documentation_2019/en/compiler_c/ps2019/get_started_lc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Linux*.

The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility, but is well suited for such usage.  See Using Environment Modules with Intel Development Tools for further information.

Back to top

Documentation

Product documentation is linked from <install-dir>/documentation_2019/en/compiler_c/ps2019/get_started_lc.htm.  Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Offline Core Documentation Removed from the Installed Image

Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.

Japanese Language Support

Intel® compilers optionally provide support for Japanese language users when the combined English-Japanese product is installed. Error messages, visual development environment dialogs and some documentation are provided in Japanese in addition to English. By default, the language of error messages and dialogs matches that of your operating system language selection. 

Japanese language support is provided with update 1 of the product.

Back to top

Intel-provided debug solutions

Back to top

Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials

Back to top

Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/ 
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

Back to top

New and Changed Features

The following features are new or significantly enhanced in this version.  For more information on these features, please refer to the documentation.

Value safe simd options for #pragma omp simd

Currently "#pragma omp simd" overrides FP value and exception safe settings. The following options change that legacy behaviour and produce value and exception safe code even for SIMD loops.

 

  • Qsimd-honor-fp-model[-]: Tells the compiler to obey the selected floating-point model when vectorizing SIMD loops
  • Qsimd-serialize-fp-reduction[-]: Tells the compiler to serialize floating-point reduction when vectorizing SIMD loops.


OpenMP SIMD specification and FP model flag can contradict in the requirement. Compiler’s default is to follow OpenMP specification and vectorize the loop. With this new flag, programmer can override so that the compiler follows the FP model flag instead and serialize the loop
Note1: When –qsimd-honor-fp-model is used and OpenMP SIMD reduction specification is the only thing causing serialization of entire loop addition of qsimd-serialize-fp-reduction will result in vectorization of the entire loop except reduction calculation which will be serialized.
Note2: This option does not affect auto-vectorization of loops.

 

New code names are to be supported in -[Q]x / -[Q]ax / -[m]tune / -[m]arch options.

code names supported :cascadelake, kabylake, coffeelake, amberlake, whiskeylake.

Custom memory allocator library

A new library "libqkmalloc" library is provided in the Intel C++ compiler 19.0 update 1. It provides a C level interface "qkmalloc()" for memory allocation. This allocation would replace standard routines.

  • void* malloc(size_t size)
  • void free(void* ptr)
  • void* calloc(size_t nobj, size_t size)
  • void* realloc(void* ptr, size_t size)

It also provides non C99 standard compliant memory allocation routine, which uses "weak" alignment void* _wmalloc(size_t size)
To use the library -

  • Set the libqkmalloc.so path to the LD_PRELOAD =$INSTALL_DIR/compiler/linux/libqkmalloc.so
  • Alternatively, define the linker option. Add -L and –l to indicate location and name of the library -L$QKMALLOC_LIB_PATH -lqkmalloc. Set up LD_LIBRARY_PATH environment variable at runtime to the library path (LD_LIBRARY_PATH="$LD_LIBRARY_PATH:$QKMALLOC_LIB_PATH"). 

Note:Non-Intel microprocessors runs the standard system malloc.

 

nodynamic_align and vectorlength clauses for pragma vector

  • Explicit syntax for dynamic alignment
    #pragma vector dynamic_align[(pointer)] #pragma vector nodynamic_align

    With no pointer specified, compiler behaves normally (automatically decides which pointer has to be aligned or doesn’t generate peel loop at all). With pointer specified, compiler generates peel loop for that pointer. With nodynamic_align clause, the compiler will not generate a peel loop.

  • #pragma vector vectorlength(vl1,vl2, .. , vln)
    #pragma vector vectorlength(vl1,vl2, .. , vln)

    Vectorizer chooses best vector length from the list according to cost model. If all vector length from the list are not profitable, the loop remains scalar. This pragma doesn’t force vectorization, thus it can be safely used for all loops.

Features from OpenMP* TR7 Version 5.0 Draft

Language features from the OpenMP* Technical Report 6 : Version 5.0 Preview 2 specifications are now supported.

  • Explicit syntax for inclusive scan *
    #pragma omp simd reduction[parallel](inscan, operator:list)
    #pragma omp scan inclusive(item-list)
  • Explicit syntax for exclusive scan *
    #pragma omp simd reduction[parallel](inscan, operator:list)
    #pragma omp scan exclusive(item-list)

    Prefix sum is computed correctly during vector execution
  • UDI for OpenMP* Parallel pragmas
    #pragma omp declare induction ( induction-id : induction-type :step-type : inductor ) [collector( collector )]

For more information, see the compiler documentation or the link to the OpenMP* Specification above.

C++17 features supported

The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/OS X*) options:

C++14 features supported

The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++14 (Windows*) or -std=c++14 (Linux*/OS X*) options:

C++11 features supported

The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++11 (Windows*) or -std=c++11 (Linux*/OS X*) options:

C11 features supported

The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/OS X*) options:

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.

  • -qopenmp-simd set by default
  • New -xcannonlake option
  • New -mtune=cannonlake option
  • -rcd option enabled “fast” float-to-integer conversions, by using round-to-nearest instead of truncating rounding. This option has been deprecated.

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.

Back to top

Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

Features/APi changes

  • More algorithms support parallel and vector execution policies: find_first_of, is_heap, is_heap_until, replace, replace_if.
  • More algorithms support vector execution policies: remove, remove_if.
  • More algorithms support parallel execution policies: partial_sort.

To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl

Support Deprecated

Intel® Cilk™ Plus deprecated in 18.0

Intel® Cilk™ Plus is a deprecated feature since Intel® C++ Compiler 18.0. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus

Support Removed

Offload support for Intel® Graphics Technology has been removed

Back to top

Known Limitations

Parallel STL

unseq and par_unseq policies only have effect with compilers that support '#pragma omp simd' or '#pragma simd. Parallel and vector execution is only supported for a subset of algorithms if random access iterators are provided, while for the rest execution will remain serial. Depending on a compiler, zip_iterator may not work with unseq and par_unseq policies.

Pointer Checker requires a dynamic runtime library

When using the -check-pointers option, the runtime library libchkp.so must be linked in. When using options like -static or -static-intel with -check-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at Pointer Checker in ICC for more information.

Back to top

Disclaimer and Legal Information

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to:  http://www.intel.com/design/literature.htm 

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: 

http://www.intel.com/products/processor%5Fnumber/

The Intel® C++ Compiler is provided under Intel’s End User License Agreement (EULA). 

Please consult the licenses included in the distribution for details.

Intel, Intel logo, Pentium, Core, Atom, Iris, Intel® Xeon®, Intel® Xeon Phi are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2018 Intel Corporation. All Rights Reserved.

Back to top

 
For more complete information about compiler optimizations, see our Optimization Notice.