Intel C++ Compiler 19.0 for macOS* Release Notes for Intel Parallel Studio XE 2019
Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 19.0
- Change History
- System Requirements
- How to Use
- Intel-provided debug solutions
- Redistributable Libraries
- Technical Support
- New and Changed Features in 19.0
- Parallel STL for parallel and vector execution of the C++ STL
- Support removed
- Known Limitations
- Disclaimer and Legal Information
This section highlights important from the previous product version and changes in product updates.
Changes since Intel® C++ Compiler 19.0.2 (New in Intel® C++ Compiler 19.0.3)
- Support for Xcode 10.1
- Integration support with the latest minor versions of supported Xcode
- Corrections to reported problems
Changes since Intel® C++ Compiler 19.0.1 (New in Intel® C++ Compiler 19.0.2)
- Intel® C++ Compiler 19.0 Update 2 includes functional and security updates. Users should update to the latest version.
Changes since Intel® C++ Compiler 19.0 (New in Intel® C++ Compiler 19.0.1)
- Value safe simd options for #pragma omp simd
- New code names are to be supported in -[Q]x / -[Q]ax / -[m]tune / -[m]arch options.
- macOS* 10.14 and Xcode* 10 support
- Corrections to reported problems
Changes since Intel® C++ Compiler 18.0 (New in Intel® C++ Compiler 19.0 )
- Support for user defined induction for OpenMP* parallel pragmas
- Support for exclusive scan simd
- -Qopenmp-simd set by default
- -rcd option deprecated
- support for cannonlake option
- support removed for 32 applications on macOS
- Changes to mitigate speculative executive side channel and new -mindirect-branch option. Please see detailed article at Using Intel® Compilers to Mitigate Speculative Execution Side-Channel Issues available at https://software.intel.com/en-us/articles/using-intel-compilers-to-mitigate-speculative-execution-side-channel-issues)
- New C++17 features supported
- Expanded partial support for OpenMP* TR6 Version 5.0 Preview 2
- New and changed compiler options
- A 64-bit Intel®-based Apple* Mac* system host
- 2GB RAM minimum, 4GB RAM recommended
- 3GB free disk space
- One of the following combinations of mac OS*, Xcode* and the Xcode SDK:
- macOS* 10.13, macOS* 10.14
- Xcode* 9.4,Xcode* 10
- If doing command line development, the Command Line Tools component of Xcode* is required
Note: Advanced optimization options or very large programs may require additional resources such as memory or disk space.
Parallel Studio XE 2019 : Getting Started with the Intel® C++ Compiler 19.0 for mac OS* at <install_dir>/documentation_2019/en/compiler_c/ps2019/get_started_mc.htm contains information on how to use the Intel® C++ Compiler from the command line and from Xcode*.
Product documentation is linked from <install-dir>/documentation_2019/en/compiler_c/ps2019/get_started_mc.htm. Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.
Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.
- Intel®-provided debug solutions are based GNU* GDB. Please see Intel® Parallel Studio XE 2019 Composer Edition C++ - Debug Solutions Release Notes further information.
Product samples are now available online at Intel® Software Product Samples and Tutorials
Refer to the Redistributable Libraries for Intel® Parallel Studio XE for more information.
If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.
For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.
Please refer here for more details.
Currently "#pragma omp simd" overrides FP value and exception safe settings. The following options change that legacy behaviour and produce value and exception safe code even for SIMD loops.
- Qsimd-honor-fp-model[-]: Tells the compiler to obey the selected floating-point model when vectorizing SIMD loops
- Qsimd-serialize-fp-reduction[-]: Tells the compiler to serialize floating-point reduction when vectorizing SIMD loops.
OpenMP SIMD specification and FP model flag can contradict in the requirement. Compiler’s default is to follow OpenMP specification and vectorize the loop. With this new flag, programmer can override so that the compiler follows the FP model flag instead and serialize the loop
Note1: When –qsimd-honor-fp-model is used and OpenMP SIMD reduction specification is the only thing causing serialization of entire loop addition of qsimd-serialize-fp-reduction will result in vectorization of the entire loop except reduction calculation which will be serialized.
Note2: This option does not affect auto-vectorization of loops.
code names supported :cascadelake, kabylake, coffeelake, amberlake, whiskeylake.
- Explicit syntax for dynamic alignment
#pragma vector dynamic_align[(pointer)] #pragma vector nodynamic_align
With no pointer specified, compiler behaves normally (automatically decides which pointer has to be aligned or doesn’t generate peel loop at all). With pointer specified, compiler generates peel loop for that pointer. With nodynamic_align clause, the compiler will not generate a peel loop.
- #pragma vector vectorlength(vl1,vl2, .. , vln)
#pragma vector vectorlength(vl1,vl2, .. , vln)
Vectorizer chooses best vector length from the list according to cost model. If all vector length from the list are not profitable, the loop remains scalar. This pragma doesn’t force vectorization, thus it can be safely used for all loops.
Language features from the OpenMP* Technical Report 6 : Version 5.0 Preview 2 specifications are now supported.
- Explicit syntax for inclusive scan *
#pragma omp simd[parallel] scan(scan-op: item-list)
#pragma omp inclusive_scan(item-list)
- Explicit syntax for exclusive scan *
#pragma omp simd[parallel] scan(scan-op: item-list)
#pragma omp inclusive_scan(item-list)
Prefix sum is computed correctly during vector execution
*The syntax will be renamed in product release
- UDI for OpenMP* Parallel pragmas
#pragma omp declare induction ( induction-id : induction-type :step-type : inductor ) [collector( collector )]
For more information, see the compiler documentation or the link to the OpenMP* Specification above.
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:
- Fold expressions(N4295)
- Inline variables(P0386R2)
- Construction rules for enum classes(P0138R2)
- Removing deprecated dynamic exception specifications(P0003R5)
- Make exception specifications part of the type system(P0012R1)
- constexpr lambda expressions(P0170R1)
- Lambda capture of *this(P0018R3)
- constexpr if-statements(P0292R2)
- Structured bindings(P0217R3)
- Separate variable and condition for if and switch(P0305R1)
- Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++14 (Windows*) or -std=c++14 (Linux*/macOS*) options:
- Please see C++14 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++11 (Windows*) or -std=c++11 (Linux*/macOS*) options:
- Please see C++11 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:
- Please see C11 Support in Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.
- -qopenmp-simd set by default
- Canary bytes are cleared right after read with /GS by default/
- New -xcannonlake option
- New -mtune=cannonlake option
- -rcd option enabled “fast” float-to-integer conversions, by using round-to-nearest instead of truncating rounding. This option has been deprecated.
For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler19.0 User's Guide.
Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.
- More algorithms support parallel and vector execution policies: find_first_of, is_heap, is_heap_until, replace, replace_if.
- More algorithms support vector execution policies: remove, remove_if.
- More algorithms support parallel execution policies: partial_sort.
To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl
Intel® Cilk™ Plus is a deprecated feature since Intel® C++ Compiler 18.0. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus
Removed support for 32 bit applications on macOS
Starting with the 19.0 release of the Intel® Fortran Compiler, macOS 32-bit applications are no longer supported. If you want to compile 32-bit applications, you should use an earlier version of the compiler and Xcode* 9.4 or earlier.
Xcode 10 new build system not supported
The Xcode 10 Beta introduced a “New Build System (Default)” which currently do not support custom compilers.You will see the error "no rule to process file" when building an Intel C++ Compiler project within XCode 10 To use Intel compilers, switch to “Legacy Build System” in Project Settings.
unseq and par_unseq policies only have effect with compilers that support '#pragma omp simd' or '#pragma simd. Parallel and vector execution is only supported for a subset of algorithms if random access iterators are provided, while for the rest execution will remain serial. Depending on a compiler, zip_iterator may not work with unseq and par_unseq policies.
For building from Xcode*, you may run into problems building the build_with_tbb configuration with llvm gcc*. The problem will be that the libtbb.dylib cannot be found. In this case, go to the Summary->Linked Frameworks and Libraries section, and manually add the libtbb.dylib library from the <install-dir>/tbb/lib directory
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to:
The Intel® C++ Compiler is provided under Intel's End User License Agreement (EULA).
Please consult the licenses included in the distribution for details.
Intel, Intel logo, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2018 Intel Corporation. All Rights Reserved.