Is there an IPP function to detect the processor type?

In Intel IPP, there is a new function named ippGetCpuFeatures() (*) that can be used to detect your processor features. It is declared in ippcore.h. This function retrieves CPU features like those returned by the Linux function CPUID.1 and stores them consecutively in the mask pFeaturesMask. The following table lists features stored in the mask. Mask values are defined in the ippdefs.h file.

Note as of version 2018, the IPP library supports the new Intel® Advanced Vector Extensions 512( Intel® AVX-512) instruction.



 Please refer to Intel IPP developer reference guide for latest processor.

Note that the legacy IPP function ippGetCpuType() (**) mixed CPU types and SIMD instruction types. Starting with version 6.0 of the library we strongly recommend using this new function ippGetCpuFeatures() to detect the CPU feature.

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Notice revision #20110804

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>>...Note that the legacy IPP function ippGetCpuType() mixed CPU types and SIMD instruction types...

This is how it looked like:

typedef enum // IPP's List of Supported Processors & Features
ippCpuUnknown = 0x00,
ippCpuPP = 0x01, // Intel(R) Pentium(R) processor
ippCpuPMX = 0x02, // Pentium(R) processor with MMX(TM) technology
ippCpuPPR = 0x03, // Pentium(R) Pro processor
ippCpuPII = 0x04, // Pentium(R) II processor
ippCpuPIII = 0x05, // Pentium(R) III processor and Pentium(R) III Xeon(R) processor
ippCpuP4 = 0x06, // Pentium(R) 4 processor and Intel(R) Xeon(R) processor
ippCpuP4HT = 0x07, // Pentium(R) 4 processor with HT Technology
ippCpuP4HT2 = 0x08, // Pentium(R) 4 processor with Streaming SIMD Extensions 3
ippCpuCentrino = 0x09, // Intel(R) Centrino(TM) Mobile Technology
ippCpuCoreSolo = 0x0a, // Intel(R) Core(TM) Solo processor
ippCpuCoreDuo = 0x0b, // Intel(R) Core(TM) Duo processor
ippCpuITP = 0x10, // Intel(R) Itanium(R) processor
ippCpuITP2 = 0x11, // Intel(R) Itanium(R) 2 processor
ippCpuEM64T = 0x20, // Intel(R) 64 Instruction Set Architecture (ISA)
ippCpuC2D = 0x21, // Intel(R) Core(TM) 2 Duo processor
ippCpuC2Q = 0x22, // Intel(R) Core(TM) 2 Quad processor
ippCpuPenryn = 0x23, // Intel(R) Core(TM) 2 processor with Intel(R) SSE4.1
ippCpuBonnell = 0x24, // Intel(R) Atom(TM) processor
ippCpuNehalem = 0x25, // Intel(R) Core(TM) i7 processor
ippCpuNext = 0x26,
ippCpuSSE = 0x40, // Processor supports Streaming SIMD Extensions instruction set
ippCpuSSE2 = 0x41, // Processor supports Streaming SIMD Extensions 2 instruction set
ippCpuSSE3 = 0x42, // Processor supports Streaming SIMD Extensions 3 instruction set
ippCpuSSSE3 = 0x43, // Processor supports Supplemental Streaming SIMD Extension 3 instruction set
ippCpuSSE41 = 0x44, // Processor supports Streaming SIMD Extensions 4.1 instruction set
ippCpuSSE42 = 0x45, // Processor supports Streaming SIMD Extensions 4.2 instruction set
ippCpuAVX = 0x46, // Processor supports Advanced Vector Extensions instruction set
ippCpuAES = 0x47, // Processor supports AES New Instructions
ippCpuX8664 = 0x60 // Processor supports 64 bit extension
} IppCpuType;

Can you see that CPUs and Features of CPUs are mixed?

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