Intel® IPP Functions Optimized for Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

Below is the list of Intel® Integrated Performance Primitives (Intel® IPP) functions that are optimized for Intel® Advanced Vector Extensions 512 (Intel® AVX-512). Among these functions, about 200 functions are optimized  for Intel® Xeon Phi™ processor x200 (codename Knights Landing) and 300 for Intel® Xeon® processor codename Skylake.  Please notes the table below represents the Intel IPP library functions that have been "hand-tuned" for optimal performance. Intel IPP functions that are not listed here can also get optimization benefit from Intel® Compiler. 

Intel® AVX-512 optimization for Intel® Xeon Phi™ processor x200 (codename Knights Landing)

ippsAddC_32fippiAddC_32f_C1R
ippsAdd_32f_IippiAddC_32f_C3R
ippsAdd_32fippiSubC_32f_C1R
ippsAdd_32fc_IippiSubC_32f_C3R
ippsAdd_32fcippiMulC_32f_C1R
ippsMul_32f_IippiAddC_32f_C1IR
ippsMul_32fippiAdd_32f_C1IR
ippsMul_32fc_IippiAdd_32f_C1R
ippsMul_32fcippiSub_32f_C1R
ippsMul_64f_IippiMul_32f_C1R
ippsMul_64fippiDiv_32f_C1R
ippsMul_64fc_IippiDivC_32f_C1R
ippsMul_64fcippiSqrt_32f_C1R
ippsSubC_32f_IippiDotProd_32f64f_C1R
ippsSubC_32fippiDotProd_32f64f_C3R
ippsSubC_32fc_IippiDotProd_32f64f_C4R
ippsSubC_32fcippiMulPack_32f_C3R
ippsSubC_64f_IippiMirror_32f_C1R
ippsSubC_64fippiNorm_Inf_32f_C1R
ippsSubC_64fc_IippiNorm_Inf_32f_C3R
ippsSubC_64fcippiNorm_Inf_32f_C4R
ippsSub_32f_IippiNorm_L1_32f_C1R
ippsSub_32fippiNorm_L1_32f_C3R
ippsSub_32fc_IippiNorm_L1_32f_C4R
ippsSub_32fcippiNorm_L2_32f_C1R
ippsSub_64f_IippiNorm_L2_32f_C3R
ippsSub_64fippiNorm_L2_32f_C4R
ippsSub_64fc_IippiNormDiff_Inf_32f_C1R
ippsSub_64fcippiNormDiff_Inf_32f_C3R
ippsDivC_32fcippiNormDiff_Inf_32f_C4R
ippsDivC_64fcippiNormDiff_L1_32f_C1R
ippsDiv_32f_IippiNormDiff_L1_32f_C3R
ippsDiv_32fippiNormDiff_L1_32f_C4R
ippsDiv_32fc_IippiNormDiff_L2_32f_C1R
ippsDiv_32fcippiNormDiff_L2_32f_C3R
ippsDiv_64f_IippiNormDiff_L2_32f_C4R
ippsDiv_64fippiNormRel_Inf_32f_C1R
ippsSqrt_32fippiNormRel_L1_32f_C1R
ippsDotProd_16s32fippiNormRel_L2_32f_C1R
ippsDotProd_32fippiSum_32f_C1R
ippsDotProd_32fcippiSum_32f_C3R
ippsDotProd_32f32fcippiSum_32f_C4R
ippsDotProd_64fcippiMean_32f_C1R
ippsDotProd_64f64fcippiMean_32f_C3R
ippsAutoCorrNorm_32fippiMean_32f_C4R
ippsAutoCorrNorm_64fippiHistogram_32f_C1R
ippsAutoCorrNorm_32fcippiFilterMedianBorder_32f_C1R
ippsAutoCorrNorm_64fcippiFilterMaxBorder_32f_C1R
ippsCrossCorrNorm_32fippiFilterMinBorder_32f_C1R
ippsCrossCorrNorm_64fippiFilterBoxBorder_32f_C1R
ippsCrossCorrNorm_32fcippiFilterBoxBorder_32f_C3R
ippsCrossCorrNorm_64fcippiFilterBoxBorder_32f_C4R
ippsConvolve_32fippiFilterSobelHorizBorder_32f_C1R
ippsConvolve_64fippiFilterScharrVertMaskBorder_32f_C1R
ippsFIRSR_32fippiFilterScharrHorizMaskBorder_32f_C1R
ippsFIRSR_32fcippiFilterSobelVertSecondBorder_32f_C1R
ippsFIRSR_64fcippiFilterSobelHorizSecondBorder_32f_C1R
ippsFIRLMS_32fippiFilterSobelNegVertBorder_32f_C1R
ippsIIR_32fippiConv_32f_C1R
ippsIIR_32fcippiCrossCorrNorm_32f_C1R
ippiAdd_32f_C1IMRippiThreshold_32f_C1R
ippiAddSquare_32f_C1IRippiThreshold_GT_32f_C1R
ippiAddSquare_32f_C1IMRippiThreshold_LT_32f_C1R
ippiAddProduct_32f_C1IRippiThreshold_Val_32f_C1R
ippiAddProduct_32f_C1IMRippiThreshold_GTVal_32f_C1R
ippiAddWeighted_32f_C1IRippiThreshold_LTVal_32f_C1R
ippiAddWeighted_32f_C1IMRippiThreshold_LTValGTVal_32f_C1R
ippiAbsDiff_32f_C1RippiCopyReplicateBorder_32f_C1R
ippiDilateBorder_32f_C1RippiCopyConstBorder_32f_C1R
ippiDilateBorder_32f_C3RippiCopyMirrorBorder_32f_C1R
ippiDilateBorder_32f_C4RippiSwapChannels_32f_C3R
ippiErodeBorder_32f_C1RippiSwapChannels_32f_AC4R
ippiErodeBorder_32f_C3RippiSwapChannels_32f_C3C4R
ippiErodeBorder_32f_C4RippiSwapChannels_32f_C4C3R
ippiFilterRowBorderPipeline_32f_C1RippiMin_32f_C1R
ippiFilterRowBorderPipeline_32f_C3RippiMax_32f_C1R
ippiFilterColumnPipeline_32f_C1RippiMinEvery_32f_C1R
ippiMinMaxIndx_32f_C1RippiMaxEvery_32f_C1R
ippiMinMaxIndx_32f_C1MRippiCompare_32f_C1R
ippiNorm_Inf_32f_C1MRippiCompare_32f_C3R
ippiNorm_Inf_32f_C3CMRippiCompare_32f_C4R
ippiNormDiff_Inf_32f_C1MRippiFilter_64f_C1R
ippiNormDiff_Inf_32f_C3CMRippiFilterBorder_32f_C1R
ippiNormRel_Inf_32f_C1MRippiGradientVectorSobel_32f_C1R
ippiNorm_L1_32f_C1MRippiGradientVectorScharr_32f_C1R
ippiNorm_L1_32f_C3CMRippiGradientVectorPrewitt_32f_C1R
ippiNormDiff_L1_32f_C1MRippiSumWindow_32f_C1R
ippiNormDiff_L1_32f_C3CMRippiSumWindow_32f_C3R
ippiNormRel_L1_32f_C1MRippiSumWindow_32f_C4R
ippiNorm_L2_32f_C1MRippiSumWindow_32f_AC4R
ippiNorm_L2_32f_C3CMRippiFilterGaussianBorder_32f_C1R
ippiNormDiff_L2_32f_C1MR 
ippiNormDiff_L2_32f_C3CMR
ippiNormRel_L2_32f_C1MR 

The functions are optimized for Intel® Xeon® processor code name Skylake

ippsAdd_32f_IippiAddC_32f_C1R
ippsAdd_32fippiAddC_32f_C3R
ippsAdd_32fc_IippiSubC_32f_C3R
ippsAdd_32fcippiMulC_32f_C1R
ippsMul_32f_IippiAddC_32f_C1IR
ippsMul_32fippiAdd_32f_C1IR
ippsMul_32fc_IippiAdd_32f_C1R
ippsMul_32fcippiMul_32f_C1R
ippsMul_64f_IippiDiv_32f_C1R
ippsMul_64fippiDivC_32f_C1R
ippsMul_64fc_IippiSqrt_32f_C1R
ippsMul_64fcippiDotProd_8u64f_C1R
ippsSubC_32f_IippiDotProd_16u64f_C1R
ippsSubC_32fippiDotProd_16s64f_C1R
ippsSubC_32fc_IippiDotProd_32f64f_C1R
ippsSubC_32fcippiDotProd_32f64f_C3R
ippsSubC_64f_IippiDotProd_32f64f_C4R
ippsSubC_64fippiMulPack_32f_C3R
ippsSubC_64fc_IippiMirror_32f_C1R
ippsSubC_64fcippiNorm_Inf_32f_C1R
ippsSub_32f_IippiNorm_Inf_32f_C3R
ippsSub_32fippiNorm_Inf_32f_C4R
ippsSub_32fc_IippiNorm_L1_32f_C1R
ippsSub_32fcippiNorm_L1_32f_C3R
ippsSub_64f_IippiNorm_L1_32f_C4R
ippsSub_64fippiNorm_L2_32f_C1R
ippsSub_64fc_IippiNorm_L2_32f_C3R
ippsSub_64fcippiNorm_L2_32f_C4R
ippsDivC_32fcippiNormDiff_Inf_32f_C1R
ippsDivC_64fcippiNormDiff_Inf_32f_C3R
ippsDiv_32f_IippiNormDiff_Inf_32f_C4R
ippsDiv_32fippiNormDiff_L1_32f_C1R
ippsDiv_32fc_IippiNormDiff_L1_32f_C3R
ippsDiv_32fcippiNormDiff_L1_32f_C4R
ippsDiv_64f_IippiNormDiff_L2_32f_C1R
ippsDiv_64fippiNormDiff_L2_32f_C3R
ippsSqrt_32fippiNormDiff_L2_32f_C4R
ippsDotProd_32fippiNormRel_Inf_32f_C1R
ippsDotProd_32fcippiNormRel_L1_32f_C1R
ippsDotProd_32f32fcippiNormRel_L2_32f_C1R
ippsDotProd_64fcippiSum_32f_C1R
ippsDotProd_64f64fcippiSum_32f_C3R
ippsAutoCorrNorm_32fippiSum_32f_C4R
ippsAutoCorrNorm_64fippiMean_8u_C1R
ippsAutoCorrNorm_32fcippiMean_16s_C1R
ippsAutoCorrNorm_64fcippiMean_16u_C1R
ippsCrossCorrNorm_32fippiMean_32f_C1R
ippsCrossCorrNorm_64fippiMean_32f_C3R
ippsCrossCorrNorm_32fcippiMean_32f_C4R
ippsCrossCorrNorm_64fcippiHistogram_32f_C1R
ippsConvolve_32fippiFilterMedianBorder_8u_C1R
ippsConvolve_64fippiFilterMedianBorder_16s_C1R
ippsFIRSR_32fippiFilterMedianBorder_16u_C1R
ippsFIRSR_32fcippiFilterMedianBorder_32f_C1R
ippsFIRSR_64fcippiFilterMaxBorder_8u_C1R
ippsFIRLMS_32fippiFilterMaxBorder_32f_C1R
ippsIIR_32fippiFilterMinBorder_32f_C1R
ippsIIR_32fcippiFilterBoxBorder_32f_C1R
ippsFFTFwd_CToC_32fcippiFilterBoxBorder_32f_C3R
ippsFFTInv_CToC_32fcippiFilterBoxBorder_32f_C4R
ippsFFTFwd_CToC_64fcippiFilterBoxBorder_16u_C1R
ippsFFTInv_CToC_64fcippiFilterBoxBorder_16s_C1R
ippsFFTFwd_CToC_32fc_IippiFilterBoxBorder_8u_C1R
ippsFFTInv_CToC_32fc_IippiFilterSobelHorizBorder_32f_C1R
ippsFFTFwd_CToC_64fc_IippiFilterScharrVertMaskBorder_32f_C1R
ippsFFTInv_CToC_64fc_IippiFilterScharrHorizMaskBorder_32f_C1R
ippsFFTFwd_CToC_32f_IippiFilterSobelVertSecondBorder_32f_C1R
ippsFFTInv_CToC_32f_IippiFilterSobelHorizSecondBorder_32f_C1R
ippsFFTFwd_CToC_64f_IippiFilterSobelNegVertBorder_32f_C1R
ippsFFTInv_CToC_64f_IippiConv_32f_C1R
ippsFFTFwd_CToC_32fippiConv_16s_C1R
ippsFFTInv_CToC_32fippiConv_8u_C1R
ippsFFTFwd_CToC_64fippiCrossCorrNorm_32f_C1R
ippsFFTInv_CToC_64fippiThreshold_32f_C1R
ippiAdd_32f_C1IMRippiThreshold_GT_32f_C1R
ippiAddSquare_32f_C1IRippiThreshold_GT_16u_C1R
ippiAddSquare_32f_C1IMRippiThreshold_GT_16u_C1IR
ippiAddProduct_32f_C1IRippiThreshold_LT_8u_C1R
ippiAddProduct_32f_C1IMRippiThreshold_LT_16s_C1R
ippiAddWeighted_32f_C1IRippiThreshold_LT_32f_C1R
ippiAddWeighted_32f_C1IMRippiThreshold_LT_8u_C1IR
ippiAbsDiff_32f_C1RippiThreshold_LT_16s_C1IR
ippiDilateBorder_32f_C1RippiThreshold_LT_16u_C1R
ippiDilateBorder_32f_C3RippiThreshold_LT_16u_C1IR
ippiDilateBorder_32f_C4RippiThreshold_Val_8u_C1R
ippiErodeBorder_32f_C1RippiThreshold_Val_16s_C1R
ippiErodeBorder_32f_C3RippiThreshold_Val_32f_C1R
ippiErodeBorder_32f_C4RippiThreshold_Val_8u_C1IR
ippiFilterRowBorderPipeline_32f_C1RippiThreshold_Val_16s_C1IR
ippiFilterRowBorderPipeline_32f_C3RippiThreshold_Val_16u_C1R
ippiFilterColumnPipeline_32f_C1RippiThreshold_Val_16u_C1IR
ippiMinMaxIndx_32f_C1RippiThreshold_GTVal_8u_C1R
ippiMinMaxIndx_32f_C1MRippiThreshold_GTVal_16s_C1R
ippiNorm_Inf_32f_C1MRippiThreshold_GTVal_32f_C1R
ippiNorm_Inf_32f_C3CMRippiThreshold_GTVal_8u_C1IR
ippiNormDiff_Inf_32f_C1MRippiThreshold_GTVal_16s_C1IR
ippiNormDiff_Inf_32f_C3CMRippiThreshold_GTVal_16u_C1R
ippiNormRel_Inf_32f_C1MRippiThreshold_GTVal_16u_C1IR
ippiNorm_L1_32f_C1MRippiThreshold_LTVal_8u_C1R
ippiNorm_L1_32f_C3CMRippiThreshold_LTVal_16s_C1R
ippiNormDiff_L1_32f_C1MRippiThreshold_LTVal_32f_C1R
ippiNormDiff_L1_32f_C3CMRippiThreshold_LTVal_8u_C1IR
ippiNormRel_L1_32f_C1MRippiThreshold_LTVal_16s_C1IR
ippiNorm_L2_32f_C1MRippiThreshold_LTVal_16u_C1R
ippiNorm_L2_32f_C3CMRippiThreshold_LTVal_16u_C1IR
ippiNormDiff_L2_32f_C1MRippiThreshold_LTValGTVal_8u_C1R
ippiNormDiff_L2_32f_C3CMRippiThreshold_LTValGTVal_16s_C1R
ippiNormRel_L2_32f_C1MRippiThreshold_LTValGTVal_32f_C1R
ippiFilterGaussianBorder_32f_C1RippiThreshold_LTValGTVal_8u_C1IR
ippiSwapChannels_32f_C3RippiThreshold_LTValGTVal_16s_C1IR
ippiSwapChannels_32f_AC4RippiThreshold_LTValGTVal_16u_C1R
ippiSwapChannels_32f_C3C4RippiThreshold_LTValGTVal_16u_C1IR
ippiSwapChannels_32f_C4C3RippiCopyReplicateBorder_8u_C1R
ippiMin_32f_C1RippiCopyReplicateBorder_16s_C1R
ippiMax_32f_C1RippiCopyReplicateBorder_16u_C1R
ippiMinEvery_32f_C1RippiCopyReplicateBorder_32f_C1R
ippiMaxEvery_32f_C1RippiCopyConstBorder_8u_C1R
ippiCompare_32f_C1RippiCopyConstBorder_8u_C3R
ippiCompare_32f_C3RippiCopyConstBorder_16s_C1R
ippiCompare_32f_C4RippiCopyConstBorder_16s_C3R
ippiFilter_64f_C1RippiCopyConstBorder_32s_C1R
ippiResizeNearest_8u_C1RippiCopyConstBorder_32s_C3R
ippiResizeNearest_8u_C3RippiCopyConstBorder_16u_C1R
ippiResizeNearest_8u_C4RippiCopyConstBorder_32f_C1R
ippiResizeLinear_8u_C3RippiCopyMirrorBorder_8u_C1R
ippiResizeCubic_8u_C3RippiCopyMirrorBorder_8u_C3R
ippiResizeLanczos_8u_C3RippiCopyMirrorBorder_8u_C4R
ippiResizeAntialiasing_8u_C3RippiCopyMirrorBorder_16s_C1R
ippiFilterBorder_8u_C1RippiCopyMirrorBorder_16s_C3R
ippiFilterBorder_32f_C1RippiCopyMirrorBorder_16s_C4R
ippiGradientVectorSobel_8u16s_C1RippiCopyMirrorBorder_32s_C1R
ippiGradientVectorSobel_16u32f_C1RippiCopyMirrorBorder_32s_C3R
ippiGradientVectorSobel_16s32f_C1RippiCopyMirrorBorder_32s_C4R
ippiGradientVectorSobel_32f_C1RippiCopyMirrorBorder_8u_C1IR
ippiGradientVectorScharr_8u16s_C1RippiCopyMirrorBorder_8u_C3IR
ippiGradientVectorScharr_16u32f_C1RippiCopyMirrorBorder_8u_C4IR
ippiGradientVectorScharr_16s32f_C1RippiCopyMirrorBorder_16s_C1IR
ippiGradientVectorScharr_32f_C1RippiCopyMirrorBorder_16s_C3IR
ippiGradientVectorPrewitt_8u16s_C1RippiCopyMirrorBorder_16s_C4IR
ippiGradientVectorPrewitt_16u32f_C1RippiCopyMirrorBorder_32s_C1IR
ippiGradientVectorPrewitt_16s32f_C1RippiCopyMirrorBorder_32s_C3IR
ippiGradientVectorPrewitt_32f_C1RippiCopyMirrorBorder_32s_C4IR
ippiGradientVectorSobel_8u16s_C3C1RippiCopyMirrorBorder_16u_C1IR
ippiGradientVectorSobel_16u32f_C3C1RippiCopyMirrorBorder_16u_C3IR
ippiGradientVectorSobel_16s32f_C3C1RippiCopyMirrorBorder_16u_C4IR
ippiGradientVectorScharr_8u16s_C3C1RippiCopyMirrorBorder_16u_C1R
ippiGradientVectorScharr_16u32f_C3C1RippiCopyMirrorBorder_16u_C3R
ippiGradientVectorScharr_16s32f_C3C1RippiCopyMirrorBorder_16u_C4R
ippiGradientVectorPrewitt_8u16s_C3C1RippiCopyMirrorBorder_32f_C1R
ippiGradientVectorPrewitt_16u32f_C3C1RippiCopyMirrorBorder_32f_C3R
ippiGradientVectorPrewitt_16s32f_C3C1RippiCopyMirrorBorder_32f_C4R
ippiSumWindow_8u32s_C1RippiCopyMirrorBorder_32f_C1IR
ippiSumWindow_16s32f_C1RippiCopyMirrorBorder_32f_C3IR
ippiSumWindow_32f_C1RippiCopyMirrorBorder_32f_C4IR
ippiSumWindow_32f_C3RippiBinToGray_1u8u_C1R
ippiSumWindow_32f_C4RippiBinToGray_1u16u_C1R
ippiSumWindow_32f_AC4RippiBinToGray_1u16s_C1R
 ippiBinToGray_1u32f_C1R
 ippiGrayToBin_8u1u_C1R
 ippiGrayToBin_16u1u_C1R
 ippiGrayToBin_16s1u_C1R
 ippiGrayToBin_32f1u_C1R

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

For more complete information about compiler optimizations, see our Optimization Notice.