Sergi Siso is a High Performance Software Engineer in the Hartree Centre, Science and Technology Facilities Council (STFC), Daresbury Laboratory, UK. He is PI of the Hartree Intel® Parallel Computing Center(s) (Intel® PCC). His main role is to analyse the performance, port and optimize scientific and technical applications to novel architectures. Complementary to his job he is coursing a PhD in the Computer Science department of the University of Liverpool, he is researching runtime systems to identify and solve performance issues on the novel many-core architectures.
The key objective of the Intel® PCC at the Hartree Centre is to enable UK academic and industrial codes to exploit the parallel and energy efficient capabilities of Intel systems, and to grow the skill base in both industry and academic institutions.
The key components of this are:
- Porting our software to utilize efficiently our new Scafell Pike system (based on Intel® microarchitecture code name Intel® Xeon® and Intel® Xeon Phi™ processors). Among the applications optimized there are:
- Unified Model and LFRic – UK Met Office Weather and Climate modelling code
- DL_POLY – Popular molecular simulation software developed at Daresbury.
- DualSPHysics: a smoothed particle hydrodynamics numerical model developed to study free-surface flows where Eulerian methods can be difficult to apply.
- DL_MESO DPD and LBE: a general-purpose mesoscale simulation package.
- Castep: code for calculating the properties of materials from first principles.
- ParaFEM: a code for parallel Finite Element Method.
- Deployment of OSPRay in Hartree’s Visualization facilities.
- Research in modern programming paradigms for high-performance computing such as Task-Based Parallelism and Embedded Domain Specific Languages.
- Assisting other Hartree Centre application specialists working on system with Intel® Xeon® and Intel® Xeon Phi™ to help them exploit performance and energy management capabilities.
- Training Education activities through one day courses to week long summer schools led by world leaders in the fields of parallel computing and Big Data analytics.
- June 28, 2018, Performance optimization for modern many-core architectures using PSyclone embedded-DSL, IXPUG ISC Workshop 2018
- Aidan Bernard Gerard Chalk, Alin Marin Elena, Luke Mason, September 14, 2017, Task Based Parallelism with OpenMP: A Case Study with DL_POLY_4, Parco2017
- Luke Mason, Rupert Ford, Chris Maynard, October 1, 2015, Optimisation of Unified Model Radiation Calculation for Xeon Phi, 9th CAWCR Workshop October 12, 2015 to October 22, 2015, Melbourne, Australia