Dr. Laura Carrington, Ph.D, is an expert in High Performance Computing. Her work has resulted in many publications in HPC application performance modeling, analysis of accelerators (i.e. FPGAs, GPUs, CPU) for scientific workloads, tools in performance analysis (i.e. processor, memory, and network simulators), benchmarking, workload analysis, and energy-efficient computing. At UCSD, she is the director of the Performance, Modeling, and Characterization (PMaC) Lab. She is in charge of Energy-efficiency thrust for the DoE SciDAC-3 Institute for Sustained Performance, Energy, and Resilience (SUPER) DoE as well as PI on a number of other awards that support the lab.
In the converging world of HPC and Big Data, and with the emergence of new storage technology, data movement is becoming a critical aspect of performance and energy efficiency. In addition, Intel’s upcoming technologies, like 3D XPoint® technology and the Intel® Xeon Phi™ coprocessor (Knights Landing), introduce complex memory sub-systems with new degrees of configuration and heterogeneity. Leveraging the different types of memory available efficiently is an optimization process that must be tackled both during the system design and in the application development. The Intel Parallel Computing Center (Intel® PCC) at PMaC lab, will focus on developing a framework to enable optimal data placement for large scale HPC and Big Data applications on systems with complex memory sub-systems based primarily on 3D XPoint memory, though applicable to the Intel® Xeon Phi coprocessor. The framework’s main component is the Advanced DAta Movement Analysis Toolkit (ADAMANT)1, which automates capturing data movement metrics for each data structure/data object allocated within a large HPC/Big Data application. The metrics include simulated data movement metrics for each data object, and for multiple memory configurations and data layouts. These metrics capture the data movement and potential impact of re-configuring the memory sub-system and/or changing the data structure’s placement within the existing configuration. The modeling component of the framework includes performance models that produce predictions based on the data structures layout in memory, and on the simulated data movement metrics for a series of configurations and data layouts. With these models, the performance optimization problem is reduced to a search for the best configuration, and the framework can inform the user of the optimal data object layout for that configuration. This insight into the performance and the behavior of an application enables users to devise optimal data layouts even on complex memory sub-systems.
The Intel® PCC at PMaC Lab will continue to harden the framework built upon ADAMANT and the features to automate the data layout and configurations optimization strategies for 3D XPoint memory. In addition, we will continue to apply ADAMANT to a series of scientific applications of interest to SDSC and the research community. Finally, we will develop adaptors that enable the interoperability of the framework with Intel performance analysis tools.
3D XPoint is a trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries.