Intel® 64 and IA-32 Architectures Software Developer Manuals

SDM

These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 architectures.

Combined Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals
Four-Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals
Ten-Volume Set of Intel® 64 and IA-32 Architectures Software Developer's Manuals
Intel® architecture instruction set extensions programming reference
Software Optimization Reference Manual
Uncore Performance Monitoring Reference Manuals
Related Specifications, Application Notes, and White Papers

Electronic versions of these documents allow you to quickly get to the information you need and print only the pages you want. The Intel® 64 and IA-32 architectures software developer's manuals are now available for download via one combined volume, a four volume set or a ten volume set. All content is identical in each set; see details below.

At present, downloadable PDFs of all volumes are at version 071. The downloadable PDF of the Intel® 64 and IA-32 architectures optimization reference manual is at version 042. Additional related specifications, application notes, and white papers are also available for download.

Note If you would like to be notified of updates to the Intel® 64 and IA-32 architectures software developer's manuals, you may utilize a third-party service, such as Visualping* to be notified of changes to this page (please reference 1 below).

Note We are no longer offering the Intel® 64 and IA-32 architectures software developer’s manuals on CD-ROM. Hard copy versions of the manual are available for purchase via a print-on-demand fulfillment model through a third-party vendor, Lulu (please reference 1 and 2 below):http://www.lulu.com/spotlight/IntelSDM.

  1. Terms of use
  2. The order price of each volume is set by the print vendor; Intel uploads the finalized master with zero royalty.

 

Combined Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals

 

DocumentDescription
Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4

This document contains the following:

Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures.

Volume 2: Includes the full instruction set reference, A-Z. Describes the format of the instruction and provides reference pages for instructions.

Volume 3: Includes the full system programming guide, parts 1, 2, 3, and 4. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX).

Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures.

Intel® 64 and IA-32 architectures software developer's manual documentation changes

Describes bug fixes made to the Intel® 64 and IA-32 architectures software developer's manual between versions.

NOTE: This change document applies to all Intel® 64 and IA-32 architectures software developer’s manual sets (combined volume set, 4 volume set, and 10 volume set).


 

Four-Volume Set of Intel® 64 and IA-32 Architectures Software Developer’s Manuals

 

This set consists of volume 1, volume 2 (combined 2A, 2B, 2C, and 2D), volume 3 (combined 3A, 3B, 3C, and 3D), and volume 4. This set allows for easier navigation of the instruction set reference and system programming guide through functional cross-volume table of contents, references, and index.

DocumentDescription
Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architecture

Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures.

Intel® 64 and IA-32 architectures software developer's manual combined volumes 2A, 2B, 2C, and 2D: Instruction set reference, A-Z

This document contains the full instruction set reference, A-Z, in one volume. Describes the format of the instruction and provides reference pages for instructions. This document allows for easy navigation of the instruction set reference through functional cross-volume table of contents, references, and index.

Intel® 64 and IA-32 architectures software developer's manual combined volumes 3A, 3B, 3C, and 3D: System programming guide

This document contains the full system programming guide, parts 1, 2, 3, and 4, in one volume. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: Memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). This document allows for easy navigation of the system programming guide through functional cross-volume table of contents, references, and index.

Intel® 64 and IA-32 architectures software developer's manual volume 4: Model-specific registers

Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures.


 

Ten-Volume Set of Intel® 64 and IA-32 Architectures Software Developer's Manuals

 

This set contains the same information as the four-volume set, but separated into ten smaller PDFs: volume 1, volume 2A, volume 2B, volume 2C, volume 2D, volume 3A, volume 3B, volume 3C, volume 3D, and volume 4. This set is better suited to those with slower connection speeds.

DocumentDescription
Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architectureDescribes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures.
Intel® 64 and IA-32 architectures software developer's manual volume 2A: Instruction set reference, A-LDescribes the format of the instruction and provides reference pages for instructions (from A to L). This volume also contains the table of contents for volumes 2A, 2B, 2C, and 2D.
Intel® 64 and IA-32 architectures software developer's manual volume 2B: Instruction set reference, M-UProvides reference pages for instructions (from M to U).
Intel® 64 and IA-32 architectures software developer's manual volume 2C: Instruction set reference, V-ZProvides reference pages for instructions (from V to Z).
Intel® 64 and IA-32 architectures software developer's manual volume 2D: Instruction set referenceIncludes the safer mode extensions reference. This volume also contains the appendices and index support for volumes 2A, 2B, 2C, and 2D.
Intel® 64 and IA-32 architectures software developer's manual volume 3A: System programming guide, part 1Describes the operating-system support environment of an IA-32 and Intel® 64 architectures, including: memory management, protection, task management, interrupt and exception handling, and multi-processor support. This volume also contains the table of contents for volumes 3A, 3B, 3C and 3D.
Intel® 64 and IA-32 architectures software developer's manual volume 3B: System programming guide, part 2Continues the coverage on system programming subjects begun in volume 3A. Volume 3B covers thermal and power management features, debugging, and performance monitoring.
Intel® 64 and IA-32 architectures software developer's manual volume 3C: System programming guide, part 3Continues the coverage on system programming subjects begun in volume 3A and volume 3B. Volume 3C covers system management mode, virtual machine extensions (VMX) instructions, and Intel® Virtualization Technology (Intel® VT).
Intel® 64 and IA-32 architectures software developer's manual volume 3D: System programming guide, part 4Volume 3D covers system programming with Intel® Software Guard Extensions (Intel® SGX). This volume also contains the appendices and indexing support for volumes 3A, 3B, 3C, and 3D.
Intel® 64 and IA-32 architectures software developer's manual volume 4: Model-specific registersDescribes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures.

 

Intel® Architecture Instruction Set Extensions Programming Reference

 

DocumentDescription
Intel® architecture instruction set extensions programming referenceThis document covers new instructions slated for future Intel® processors.

 

Software Optimization Reference Manual

 

DocumentDescription

Intel® 64 and IA-32 architectures optimization reference manual

The Intel® 64 and IA-32 architectures optimization reference manual provides information on current Intel microarchitectures. It describes code optimization techniques to enable you to tune your application for highly optimized results when run on current Intel® processors.
Intel® Xeon® Scalable Processor throughput and latencyDescribes throughput and latency for Intel® Xeon® Scalable Processor.
10th Generation Intel® Core™ Processor Instruction throughput and latencyDescribes throughput and latency for 10th Generation Intel® Core™ Processor.

 

Uncore Performance Monitoring Reference Manuals

 

Document
Intel® Xeon® Processor E7 Family Uncore Performance Monitoring Programming Guide
Intel® Xeon® Processor E5 v2 and E7 v2 Product Families Uncore Performance Monitoring Reference Manual
Intel® Xeon® Processor 7500 Series Uncore Programming Guide
Intel® Xeon® Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual
Intel® Xeon® Processor E5-2600 v2 Product Family Uncore Performance Monitoring Reference Manual
6th Generation Intel® Core™ Processor Family Uncore Performance Monitoring Reference Manual
Intel® Xeon® Processor Scalable Memory Family Uncore Performance Monitoring Reference Manual

 

Related Specifications, Application Notes, and White Papers

 

DocumentDescription
Intel Analysis of Speculative Execution Side ChannelsThis document provides an overview of the variants along with related Intel security features.
Speculative Execution Side Channel MitigationsThis document provides a detailed explanation of the security vulnerabilities and possible mitigations.
Intel® 64 and IA32 Architectures Performance Monitoring EventsPerformance monitoring events for Intel® processors.
Intel® Data Streaming Accelerator Preliminary Architecture SpecificationThis document describes the architecture of the Intel® Data Streaming Accelerator (Intel® DSA).
bfloat16 - Hardware Numerics DefinitionThis document describes the bfloat16 floating-point format.
5-Level Paging and 5-Level EPT white paperThis document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware.
MCA Enhancements in Intel® Xeon® ProcessorsThis document describes Enhanced MCA Logging software architecture and associated flows.
Timestamp-Counter Scaling for VirtualizationThe information contained in this white paper has been merged into volume 3C of the Intel® 64 and IA-32 architectures software developer's manual.
Intel® 64 architecture x2APIC specificationExtensions to the xAPIC architecture are intended primarily to increase processor addressability. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendability for future Intel platform innovations.
Intel® 64 and IA-32 architectures application note TLBs, paging-structure caches, and their invalidationThe information contained in this application note is now part of Intel® 64 and IA-32 architectures software developer's manual volumes 3A and 3B.
Intel® carry-less multiplication instruction and its usage for computing the GCM mode white paperThis paper provides information on the instruction, and its usage for computing the Galois Hash. It also provides code examples for the usage of PCLMULQDQ, together with the Intel® AES New Instructions (Intel® AES-NI) for efficient implementation of AES in Galois Counter Mode (AES-GCM).
Intel® 64 architecture memory ordering white paperThis document has been merged into Volume 3A of Intel® 64 and IA-32 architectures software developer’s manual.
Performance monitoring unit sharing guideThis paper provides a set of guidelines between multiple software agents sharing the PMU hardware on Intel® processors.
Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) application noteThis application note discusses virtualization capabilities in Intel® processors that support Intel® VT FlexMigration usages.
Intel® Virtualization Technology for
Directed I/O architecture specification
This document describes the Intel® Virtualization Technology for Directed I/O.
Intel®  Scalable I/O Virtualization Technical SpecificationThis document describes Intel® Scalable I/O Virtualization, a scalable and composable approach for virtualizing I/O devices.
Page Modification Logging for Virtual Machine Monitor white paperThe information contained in this white paper has been merged into volume 3C of the Intel® 64 and IA-32 architectures software developer's manual.
Secure Access of Performance Monitoring Unit by User Space ProfilersThis paper proposes a software mechanism targeting performance profilers which would run at user space privilege to access performance monitoring hardware. The latter requires privileged access in kernel mode, in a secure manner without causing unintended interference to the software stack.

 

For more complete information about compiler optimizations, see our Optimization Notice.

16 comments

Top

It states that latest SDM is updated on September 26, 2019, 

But the linked SDM pdf is the old one of May, 2019, did Intel forget to update the PDF file?

Any way to get a physical copy of this? That would be the ultimate flex.

roolebo@gmail.com's picture

Found a typo on the page 3-6 Vol.1: "Intel 64 architecture introduces a changes in physical and linear address space" should be "Intel 64 architecture introduces a set of changes in physical and linear address space"

Hey, i found a typo in 7.2.1 Task-State Segment (TSS)

EFLAGS register field — State of the EFAGS register prior to the task switch.

It is not obvious from the descriptions of the L2 cache sizes using CPUID(4) and CPUID(80000006h) in the software developer's manual volume 2 (325383-063US), why the two inquiry methods would return different sizes.

CPUID(80000006h) returns (eax, ebx, ecx, edx): 0 0 0x1006040 0. Documentation says that bits 31:16 of ecx is L2 cache size in K units, which translates to 256K.

The L2 cache information from CPUID(4) returns (eax, ebx, ecx, edx): 0x7c004143 0x3c0003f 0x3ff 0, which according to (heading page 3-216 Vol 2A.) "INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level" size is computed as:

This Cache Size in Bytes

= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)

= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)

Which I believe given the ebx/ecx values comes to 1048576.

/proc/cpuinfo (Linux) shows:

processor    : 0

vendor_id    : GenuineIntel

cpu family   : 6

model      : 85

model name   : Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz

stepping    : 4

microcode    : 0x200004d

cpu MHz     : 1000.000

 

My question is: which method is correct? The 1MB L2 cache size as returned by CPUID(4) seems to match with all public information for this processor/model.

 

BTW, the discrepancy in L2 sizes only seems to happen with the Skylake Xeon processor that I have access to.

Thank you.

 

Vol. 3B page 499, "101B 63.5%" should be "101B 62.5%"?

There seems to be a typo in the entry for MULPS:

Multiply the packed single-precision floating-point values (...), and stores the packed double-precision floating-point results in the destination operand.

In reality, the result should be a single-precision value, not double-precision, just like the arguments. This is corroborated by the pseudo-code for the same entry:

DEST[31:0] ← SRC1[31:0] * SRC2[31:0]

... 

There is a missing word in Vol 3C 23-1
 

Processor behavior in VMX root operation is very much as it is outside VMX operation.

This does not mean anything,  "must" should be replaced by "different"

The Resources are very good

It would be great to have it in Epub format for ebook

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