Intel Software Tools Webinar Series Archive

This free webinar series presented tools, tips, and techniques that will help sharpen your development skills on Intel processors/coprocessors including Intel® Xeon® processor and Intel® Xeon Phi™ coprocessor. Intel technical experts as well as open source innovators discuss topics ranging from compiler techniques including vectorization & OpenMP 4.0, performance libraries, debugging, error checking and tuning to boost application and platform performance. Come to the live sessions with your programming questions for Intel technical experts to answer.

Upcoming Webinars

Webinar Details Description

Parallel programming models - tips and tricks

Apr 21 9:00 A.M. Pacific

Presenter:
James Tullos

View Archive

 

As computing advances, parallel architectures are becoming more common. In order to take advantage of parallel systems, software must adapt and use more parallelism. In this webinar, I will discuss various parallel programming models for shared memory and distributed memory parallelism, and give advice for how to utilize each of these models. I will also discuss how Intel® Advisor XE, Intel® VTune™ Amplifier XE, and Intel® Trace Analyzer and Collector can assist with adding parallelism to your programs or to improve your current parallelism.

Vectorize or Die – unlock performance secrets with data driven software design

Apr 14 9:00 A.M. Pacific

Presenter:
Kevin O'leary

View Archive

 

The free ride of faster performance with increased clock speeds is long gone. Software must be both threaded and vectorized to fully utilize today’s and tomorrow’s hardware. But modernization is not without cost. Not all threading or vectorization designs are worthwhile. How do you choose which designs to implement without disrupting ongoing development? Learn how data driven threading and vectorization design can yield long term performance growth with less risk and more impact.

New Vectorization Features of the Intel Compiler

Apr 7 9:00 A.M. Pacific

Presenter:
Martyn Corden

View Archive

The vectorization features of the Intel compiler continue to get more powerful with each succeeding version. In this webinar, we will look beyond the vectorization of simple loops over intrinsic data types, to examples involving STL (Standard Template Library) vectors; indirect addressing (gathers and scatters); multi-dimensional arrays, including data alignment; and explicit outer loop vectorization, using the SIMD feature of OpenMP 4.0. Code samples will include C, C++ and Fortran.

Maximize Graphics Processor Compute Power for General Purpose Computing

12/03/2014 9:00 AM PST

Presenter:
Anoop Madhusoodhanan Prabha

View Archive

Processor graphics hardware occupies almost 30% of the processor silicon real estate. This makes it all the more important to expose these computation units to developers for general-purpose computing and unlock the idle GFLOPS in Intel® Graphics Technology. We’ll examine how the C++ offload compiler enables you to fully utilize Intel® processors through easy access to the GPGPU capabilities of Intel Graphics Technology. This compute offload feature is accomplished using the C/C++ Intel® Cilk™ Plus parallel programming paradigm with small extensions for kernel and data offload.

While it’s essential to provide compelling heterogeneous programming models for general-purpose computing, it’s also critical to simplify porting existing C/C++ applications for efficient execution on processor graphics. The Intel Cilk Plus programming model helps express the potential parallelism and vectorization opportunities in the source code. This capability is available on Win32*, Win64* and Linux64* (Ubuntu* 12.04 and SLES* 11) platforms

Increase Insight into Kernel Module Development with JTAG Debugging

11/19/2014 9:00 AM PST

Presenter:
Paul Farquhar

View Archive

 

A JTAG debugger can be a great tool in kernel module development. Advantages include halting the complete system during debugging (not only the thread being debugged), and making it easy to examine the entire CPU and memory.

We’ll look at how the Intel® System Debugger functions to debug a kernel module of Yocto* built Linux*. After loading the module symbols, we’ll debug in source code. As a target, we will use the Intel® Quark™ based platform Galileo, often used in Internet of Things (IoT) solutions. We’ll use the open source software OpenOCD* to connect to the JTAG probe.

Using a JTAG debugger is easier than you might expect and the benefits far outweigh the learning curve. Learn the steps necessary to prepare for JTAG debugging with the Intel System Debugger and the hardware support requirements.

Optimize for Energy Efficiency: Software-Based Power Analysis

11/12/2014 9:00 AM PST

Presenter:
Kevin O’leary

View Archive

A close look at software-based power analysis solutions on Intel® architecture-based systems. A key consideration when tuning for power is whether the system is waking up unnecessarily and what is causing the system to wake up from a low power state. Another factor is whether your system is operating at a high frequency—thereby consuming power at an accelerated rate. We will examine several system power issues that can greatly degrade a system and discuss potential solutions. We’ll cover power analysis on both Android* and Windows* systems. Learn the different power and frequency states of Intel® based architectures, as well as different software techniques for tuning for power.

Build and Optimize Embedded, Mobile, and Internet of Things Applications

11/05/2014 9:00 AM PST

Presenter:
Naveen Gv

View Archive

Learn how to build and optimize imaging, in-vehicle infotainment (IVI), long-term evaluation reference design, and surveillance applications on Intel® architecture using different components of Intel® System Studio.

  • Perfect printer and image processing performance on Intel architecture
  • Enhance IVI application performance and CPU utilization
  • Boost long-term evolution (LTE) application performance
  • Optimize OpenCV* based video surveillance applications

Design Code that Scales

Tue, Nov 4, 2014
9:00 AM - 10:00 AM PDT

Presenter:
Zakhar Matveev and CJ Newburn

View Archive

As systems grow in complexity due to the number and type of cores, and vector size, you need to develop and update code to ensure scalability and take advantage of current and next-gen platforms. Time to scale impacts time to market. Intel software development experts discuss application/workload scalability and how to utilize the latest tools and techniques. Topics include code suitability and predicting what happens as your workload scales, identifying potential data races and performance losses caused by imbalance, and runtime overhead and contention on highly parallel SMP platforms.

Optimizing LAMMPS* for Intel® Xeon Phi™ Coprocessors

Wed, October 29, 2014
11:00 AM - 12:00 PM PDT

Presenter:
Dr. Michael Brown

View Archive

Come learn what Intel specifically did to optimize LAMMPS to take advantage of Intel® Xeon® and Intel® Xeon® coprocessors, and about the resulting performance from those optimizations.

New Intel System Studio features include:

  • Support for the Microsoft Windows* target platforms for build, performance analysis, and energy profiling
  • Use of Intel® Processor Trace (Intel® PT) on the brand-new 5th generation Intel® Core™ M Processor to more easily identify runtime issue root causes
  • Tight Intel System Studio integration into Wind River Workbench* for a seamless development, debug, and analysis experience when targeting the latest Intel® architecture designs running Wind River Linux*
  • Compiler integration with the latest Android* NDK and tools support for the very latest Android OS features

Accelerate Development for Embedded, Mobile, and the Internet of Things

Wed, October 29, 2014
9:00 AM - 10:00 AM PDT

Presenter:
Robert Mueller

View Archive

Join us for an in-depth look at software development for embedded, mobile, and the Internet of Things. Learn how to apply the newest Intel® System Studio features to real-world development challenges. We’ll look at examples and demos of how these features speed up and streamline the development cycle based on the MinnowBoard MAX and Intel® Atom™ Processor E3800 platform.

New Intel System Studio features include:

  • Support for the Microsoft Windows* target platforms for build, performance analysis, and energy profiling
  • Use of Intel® Processor Trace (Intel® PT) on the brand-new 5th generation Intel® Core™ M Processor to more easily identify runtime issue root causes
  • Tight Intel System Studio integration into Wind River Workbench* for a seamless development, debug, and analysis experience when targeting the latest Intel® architecture designs running Wind River Linux*
  • Compiler integration with the latest Android* NDK and tools support for the very latest Android OS features

New Intel® Math Kernel Library Features Boost Performance for Tiny and Gigantic Computations

Tue, Oct 28, 2014
9:00 AM - 10:00 AM PDT

Presenter:
Vipin Kumar

View Archive

Intel® Math Kernel Library (Intel® MKL) is a computational math library aimed at unleashing performance on Intel® architecture. Designed for scientific, engineering, and financial applications, it efficiently handles both very small and very large computations. Here, we’ll introduce two new features in Intel MKL. The first, helps programmers to boost performance on a single CPU core with minimal effort when dealing with small data sets (for example, matrix multiplication for tiny matrices). The second, at the other end of the spectrum, efficiently solves large-scale sparse linear systems with tens of millions of equations on clusters. We’ll focus on usage models and APIs for these new features and share relevant performance data.

Accelerate Complex Simulations: An Example From Manufacturing

Tue, Oct 21, 201
9:00 AM - 10:00 AM PDT

Presenter:
Eric Lequiniou, Altair's Director of Engineering

View Archive

Altair's software products enable a wide range of industries to conduct complex simulations crucial to engineering innovation and deliver reliable products to market. In a sector where supporting enhanced performance and new feature sets is critical, Altair is using Intel® Software Development tools to scale on Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors as quickly as possible to improve its customers' competitive advantage. Join us as Altair's Director of Engineering, Eric Lequiniou, discusses how Intel® tools help drive application innovation to provide the best possible performance.

MPI-3 Is Here: Optimize and Perform with Intel MPI Tools

Oct 7, 2014 9:00 A.M. Pacific

Presenter:
Gergana Slavova

View Archive

Intel® Math Kernel Library (Intel® MKL) is a computational math library aimed at unleashing performance on Intel® architecture. Designed for scientific, engineering, and financial applications, it efficiently handles both very small and very large computations.

Got Errors? Need to Thread? Intel® Software Dev Tools to the Rescue

Sep 30, 2014 9:00 A.M. Pacific

Presenter:
James Tullos

View Archive

Intel® Parallel Studio XE provides the compilers and libraries needed to build fast code. The Professional Edition adds analysis and we’ll explore new features for prototyping thread designs, eliminating threading/memory errors, and tuning applications. Special topics include improved thread prototype suitability view and modeling capacity, improvements to memory growth and on-demand leak detection, and faster threading analysis. And, we've simplified Intel® Parallel Studio XE in three editions—join us and find out more.

Update Now: What’s New in Intel® Compilers and Libraries

Sep 23, 2014 9:00 A.M. Pacific

Presenter:
Ron Green

View Archive

Build fast code faster with the compilers and libraries in the new Intel® Compiler Version 15.0. We’ll examine new capabilities in the 2015 Intel compiler release, including new optimization and vectorization reports that streamline performance enhancements, increased language standards support, and useful new compiler options. And, what’s in a name? We've simplified Intel® Parallel Studio XE in three editions—join us and find out more.

Knights Corner: Your Path to Knights Landing

Sep 17, 2014 9:00 A.M. Pacific

Presenter:
James Reinders

View Archive

Join parallelism expert and evangelist James Reinders and find out how to best prepare your application for Knights Landing. The highly scalable, next-generation Intel® Xeon Phi™ processor/coprocessor will appear in late 2015, but you can get ready now for its advanced parallel processing capabilities. While it is true that programs making good use of Knights Corner will have a great path to Knights Landing, there are other options. We'll cover the paths to Knights Landing, and how to select the best path for your application. It's all about scaling and vectorization—techniques that can benefit your code today, and in the future.

Remodel your Code with Intel® Advisor XE

Jun 24 9:00 A.M. Pacific

Presenter:
Ravi Vemuri

View Archive

Thanks to the multi-core era, it has become imperative for software developers to exploit parallelism inherent in their applications. Intel® Advisor XE helps make incorporating threading into applications easier by allowing developers to model parallelism. It inculcates in software developers a disciplined approach to exploiting parallelism. Inte® Advisor XE obviates guesswork and trial-and-error based approaches, and instead guides developers to confidently model and transform serial portions of code to parallelized versions in a step by step methodical fashion.

The presenter will introduce the Intel® Advisor XE tool and demonstrate a structured approach to exploiting parallelism that Intel® Advisor XE facilitates. Attendees of this webinar will gain:

  • Understanding of the importance of approaching parallelization problems based on measured data rather than guesswork
  • The importance of performing parallelism modeling using Intel® Advisor XE annotations and analyses so that correct portions of your software can be judiciously selected and parallelized
  • Knowledge of resources, including a clear step-by-step process, for implementing threading in software

Sparse Linear Algebra Functions in Intel® Math Kernel Library

Jun 17 9:00 A.M. Pacific

Presenter:
Zhang Zhang

View Archive

Sparse matrix algorithms are encountered in a broad range of important scientific computing applications. Intel MKL offers a powerful set of functions that can be used to build a complete solution to many sparse linear systems. This webinar gives an overview on MKL's sparse linear algebra component. Highlights include Sparse BLAS functions, Direct solvers for sparse linear systems, Iterative solvers and Eigensolvers for sparse matrices based on the FEAST algorithm.

Intel MPI library implementation of a new MPI3.0 standard - new features and performance benchmarks.

Jun 10 9:00 A.M. Pacific

Presenter:
Mark Lubin

View Archive

Introduction into implementation of a new MPI-3 standard by the latest Intel MPI library 5.0. MPI 3.0 standard introduced many new features such as new one-sided (Remote Memory Access (RMA)) communication semantics, non-blocking and neighborhood  collectives, improvements in Fortran bindings and fault tolerance.   New MPI 3.0 standard targets to improve performance, reliability and ease of use of HPC cluster applications. In this webinar we will cover MPI 3.0 features implemented in Intel MPI 5.0 library (beta) illustrated by small examples codes. Complementing release of Intel MPI 5.0, we also release a new version of Intel micro-benchmarks library IMB 4.0 containing the benchmarks for non-blocking collectives and new RMA interface. To observe performance benefits with these benchmarks, the asynchronous progress support in multi-threaded version of Intel MPI 5.0 library was implemented . The preliminary performance results based on IMB 4.0 show 2x performance advantage of non-blocking collectives for medium and large message sizes. We will also demonstrate performance advantages of truly passive RMA put function invocation in IMB 4.0 test-suite. Finally, a small stencil kernel will be used to demo a new shared memory MPI API functions that can compete with hybrid MPI and OpenMP applications.

Intel® VTune™ Amplifier XE Overview and New Features

Jun 3 9:00 A.M. Pacific

Presenter:
Gary Carleton

View Archive

This webinar will give an overview of the VTune™ Amplifier XE features including: first use tips, performance collection modes (Hotspots, General Exploration, Locks-And-Waits), and tuning occasional random slowdowns. In addition, some of the VTune™ Amplifier XE's newer features will be discussed: launching a data collection remotely, Intel® Xeon Phi™ coprocessor support, tips on speeding up the analysis phase, OpenMP support, some cluster support, and Pause/Resume APIs. We will also discuss some upcoming features such as running the VTune™ Amplifier XE analysis GUI on a Mac.

An Introduction to Intel® Visual Fortran Development on Intel® Xeon Phi™ coprocessor

May 27 9:00 A.M. Pacific

Presenter:
Kevin Davis

View Archive

The Intel® Visual Fortran Composer XE SP1 release includes support for Intel® Xeon Phi™ coprocessors on Windows*. This webinar introduces the development environment for developing Fortran applications for the Intel® Xeon Phi™ coprocessor for Windows*. You will learn about the system configuration including details of the Intel® Manycore Platform Software Stack (Intel® MPSS), integrations with Microsoft Visual Studio*, Fortran offload programming models, developing and debugging offload and native applications, and existing limitations.

What’s New in the Intel® VTune™ Amplifier XE 2015 Beta release

May 22 9:00 A.M. Pacific

Presenter:
David Anderson

View Archive

Join us for a look at all the new features arriving in the 2015 Beta release of VTune Amplifier XE.

Tachyon ray tracer port on Intel® Xeon Phi™ coprocessor

May 20 9:00 A.M. Pacific

Presenter:
Roman Lygin

View Archive

This webinar will present a practical case study of porting the Tachyon, an open source ray tracer, part of the SpecMPI suite, to Intel® Xeon Phi™ coprocessor. The Initial port revealed disappointing performance, e.g. the combined Intel® Xeon® processor and Intel Xeon Phi coprocessor version ran 2.6x slower than Xeon-only version. To achieve good performance some code modifications needed to be introduced improving both processor and coprocessor parts. Intel® Cluster Studio XE is used to pinpoint the problems and will highlight key code changes which helped achieve significant improvements (up to 7x vs from initial baseline, and 1.8x speed up vs improved Xeon version). The application exploits parallelism at multiple levels - symmetric MPI execution model, OpenMP-based multi-threading, and explicit SIMD (using SSE2/AVX/Xeon Phi instructions). Several software tools will be highlighted – Intel® Trace Analyzer and Collector, and Intel® VTune™ Amplifier XE in combination with MPI* and OpenMP* programming models, as well as a SIMD-enabled 3D vector operations library (reused and extended from Embree, the open source ray tracer by Intel Labs). Algorithmic changes include MPI-based dynamic scheduling, introduction of explicit intrinsics-based SIMD support, enabling greater OpenMP parallelism capacity.

Intel® MKL 11.2 Beta Webinar - Introducing New features

May 15 2014

Presenter:
Sridevi Allam

View Archive

Join us for a look at all the new features arriving in the 2015 Beta release of MKL 11.2

Find Bugs Quickly and Easily in Your Fortran Application Using Intel® Inspector XE

May 13 9:00 A.M. Pacific

Presenter:
Jackson Marusarz

View Archive

This webinar will present the debugging and analysis capabilities of Intel® Inspector XE with a focus on Fortran development. Quickly detect and locate threading and memory issues in your application, and correlate those issues to the exact line of source code causing the problem. The presentation will include specific examples of common errors and how Intel® Inspector XE can greatly aid in the debugging process.

Flow Graph with Intel® Threading Building Blocks

May 6 9:00 A.M. Pacific

Presenter:
Kevin O'Leary

View Archive

The hardware landscape has changed from being mostly serial to mostly parallel in the past 5-10 years. A lot of effort has gone into enabling software to take advantage of the increase in computing power in modern parallel machines, but most software available today offer limited scalability. Developers have spent a lot of time adding incremental parallelism, mostly addressing the data parallel code regions, but the rest of application remains serial. A robust design of a concurrent system is applicable to many areas of engineering from embedded systems to scientific computing. Designing such systems using data?ow-oriented models can expose large amounts of concurrency to system implementation that otherwise go unharnessed. Utilizing this concurrency effectively enables distributed or parallel execution and increased throughput, or reduced power usage at the same throughput. This lecture discusses the importance of building such robust systems by mapping the actor/agent paradigm to your algorithm or code and implementing the system using the new flow graph feature introduced in Intel® Threading Building Blocks (Intel® TBB) 4.0. TBB flow graph feature allows users to easily create flow graphs and dependency graphs that execute on top of Intel TBB tasks.  Users programmatically create nodes and edges that express the computations performed by their application and the dependencies between these computations. The Intel TBB library is then able to exploit the parallelism that is implicit in the graph structure, and the resources available on the target machine, to speed up the application. Flow graphs are applicable across a wide range of domains, including media, gaming, finance, portable/low-power computing, big data analytics and technical computing. An overview of the Actor/Agent paradigm will be presented and the audience will be walked through the details of simple and complex examples that demonstrate the power and flexibility of this parallel programming abstraction.  The challenges of debugging and performance tuning of such constructs will be outlined and explored through traditional profiling techniques and a prototype tool chain.

Performance essentials using OpenMP* 4.0 vectorization with C/C++

Apr 29 9:00 A.M. Pacific

Presenters:
Bob Chesebourgh and Anoop Madhusoodhanan Prabha

View Archive

This webinar teaches you about Vectorization, what it is and why you should care about it as a software developer. It will cover terms such as SIMD and vectorization, Vector Lanes, Vector Length and discusses performance expectations per core. It will also explores the tradeoff between using compiler autovectorization versus explicit vector programming versus SIMD intrinsics and assembly. It compares explicit vector programming as being similar to explicit parallel programming using OpenMP parallelism constructs, where the developer takes control and responsibility for vectorizing specified loops. also gives quick examples of the two big ideas in explicit vector programming: omp SIMD loops, and SIMD-enabled functions enabled with the pragma omp declare simd family of constructs.

What's New in the Intel® Software Tools 2015 Beta releases

Apr 22 9:00 A.M. Pacific

Presenter:
Gergana Slavova

View Archive

Join the technical experts at Intel as they provide you with details on the new features in the Intel® Software Tools 2015 Beta releases that access the newest Intel multicore processors, manycore coprocessors, and Intel® Graphics Technology.  This technical presentation will cover new Beta features for the most recent standards: OpenMP4.0, MPI-3, Fortran 2003 and 2008, and C++ 11 running on the newest Linux*, Windows*, and OS X* operating systems.  Covered will be a new C/C++ compiler driver "icl" for OS X*.  Intel® Math Kernel Library adds Cluster PARDISO, Airmont, and Goldmont Atom optimizations, and certain tunings for the Haswell and Broadwell architectures.  Intel® VTune™ Amplifier XE additionally boast an improved ease-of-use via changes in the Summary Pane and General Exploration.  Intel® Trace Analyzer and Collector offers a brand-new performance assistant to aid in removing the bottlenecks in your MPI code.  Intel Advisor XE presents a dramatically improved suitability view. Intel Inspector XE has generated a 3X performance improvement for threading analysis and improvements to memory growth and on-demand leak detection.

Intel® Cilk™ Plus Array Notation - Technology and Case Study

Apr 15 9:00 A.M. Pacific

Presenters:
Bob Chesebourgh and Anoop Madhusoodhanan Prabha

View Archive

Vectorization plays a paramount role in speeding up programs with data parallelism inherent in their algorithms. Intel C++ Compiler provides explicit vector programming methods that can be used to achieve greater performance. Intel® Cilk™ Plus allows a developer to do explicit vectorization using Intel® Cilk Plus™ SIMD directive, Array Notation and simd-enabled functions to increase performance potential in your application. Attend this webinar to learn about this technology and see a case study of Array Notation applied to Discrete Cosine Transform (DCT) kernel.

Quickly discover performance issues with the Intel® Trace Analyzer and Collector 9.0 Beta

Apr 8 9:00 A.M. Pacific

Presenter:
Gergana Slavova

View Archive

The Intel® Trace Analyzer and Collector has a long-standing reputation as a profiler that helps you understand MPI application behavior, and effectively visualize bottlenecks in your code.  The new 9.0 Beta release introduces an even easier way to identify performance issues in your code via a brand new tool called the Performance Assistant.  Join us as we discuss how the Performance Assistant is able to analyze your code, determine potential performance problems, and suggests solutions.  We will discuss the technology and ideas behind how MPI performance bottlenecks are detected, and how you can easily implement solutions based on the information provided.

Porting and Tuning of Lattice QCD* and MPI-HMMER* for Intel® Xeon Processors & Intel® Xeon Phi™ Coprocessors

Nov 12 9:00 A.M. Pacific

Presenter:
Frances Roth

View Archive

The Intel® Xeon Phi™ architecture from Intel Corporation features parallelism at the level of many x86-based cores, multiple threads per core, and vector processing units. Lattice Quantum Chromodynamics (LQCD) is of importance in studies of nuclear and high energy physics and MPI-HMMER is an open source MPI implementation of the HMMR protein analysis suite and important to life science research. Technical experts at Intel describe the process and experience with optimizing key kernels for the Intel® Xeon Phi™ coprocessor and to achieve performance on the applications with the addition of an Intel® Xeon Phi™ coprocessor over a Intel® Xeon E5 system.

Precision Memory Leak Detection Using the New On-Demand Leak Detection in Intel® Inspector XE

Nov 6 9:00 A.M. Pacific

Presenter:
Holly Wilper

View Archive

Intel® Inspector XE now gives you the ability to set and reset memory baselines and ask for memory leak information from your program whenever you want it. You will learn how to skip analysis of sections of the code you are not interested in, how to choose whether memory growth or on-demand leak detection is the right tool for you, and how to choose the correct analysis level to use, whether you are looking for that one pesky leak or looking to set up a QA process to find future leaks.

Software Architects: Design and Prototype Scalable Threading using Intel® Advisor XE

Nov 5 9:00 A.M. Pacific

Presenter:
Ravi Kumar Vemuri

View Archive

Breakthrough techniques for threading design let architects and lead designers quickly evaluate alternative designs. Project threading performance impact for systems with from 2 to 512 cores. Learn how to quickly compare the performance scaling of alternative threading designs and find synchronization errors before investing in implementation. Evaluate alternative designs without disrupting normal development.

Finding the Right Fit for Your Application on Intel® Xeon Processors and Intel® Xeon Phi™ Coprocessors

Oct 23 9:00 A.M. Pacific

Presenter:
CJ Newburn

View Archive

Not all applications are created equal. Some are chomping at the bit to harvest as much parallelism as a target platform can provide. Those may be good candidates for running on an Intel® Xeon Phi™ Coprocessor. Other applications are scalar (not vectorized) and sequential (not threaded). They won't even make full use of an Intel Xeon processor, much less an Intel Xeon Phi Coprocessor. Before moving to a highly-parallel platform, the developer-tuner needs to expose enough parallelism to hit the limits of the Intel Xeon platform. Join us as we explore finding the right fit for applications on Intel(r) Xeon processors and Intel(r) Xeon Phi coprocessors.

Introduction to OpenMP 4.0 for SIMD and Affinity Features with Intel® Xeon® Processors and Intel® Xeon Phi™ Coprocessors

Oct 22 9:00 A.M. Pacific

Presenter:
Michael Klemm

View Archive

Continuing its long tradition of standards-based software products, Intel has implemented new OpenMP features that enhance the usage of its hardware products.  The newly-released OpenMP 4.0 specification (http://www.openmp.org) contains several features that are especially useful with Intel® Xeon Phi™ coprocessors.  The accelerator feature is a standardized way to program off-loading computations to such devices.  The SIMD feature is a standardized way to engage the 512-bit wide SIMD capability on Intel® Xeon Phi™ coprocessors.  The affinity feature gives users the ability to pin threads to cores in a new, more sophisticated way.  Taken together, these OpenMP 4.0 features can help the user maximize performance on the new Intel® Xeon Phi™ coprocessors, while at the same time always applying to standard Intel® Xeon processors, preserving your software investment.

Powered by MKL: Accelerating NumPy/SciPy and R Performance with Intel® MKL

Oct 15 9:00 A.M. Pacific

Presenters:
Zhang Zhang / Vipin Kumar

View Archive

NumPy/SciPy are scientific libraries for Python. R is a programming language for statistics computing. These tools, especially their open source packages, have gained popularity among programmers in scientific and statistic computing. A fundamental component in both NumPy/SciPy and R are the linear algebra functions, which rely on the standard BLAS and LAPACK routines. Intel® Math Kernel Library (Intel® MKL) provides a high performance implementation of BLAS and LAPACK that is optimized for Intel architectures. This webinar discusses building the open source NumPy/SciPy and R with Intel MKL to significantly improve the performance of linear algebra operations. Beyond BLAS and LAPACK, there are other functions in Intel MKL that can provide great performance benefit. This webinar will give a quick tutorial on how to extend NumPy/SciPy and R by writing a wrapper for an Intel MKL function and then use it from NumPy/SciPy or R programs.

Become a C++ Hot Spot Hotshot with Intel® Parallel Studio XE

Oct 1 9:00 A.M. Pacific

Presenter:
JD Patel

View Archive

Are you looking to boost your application performance with just a small time investment?  Look no further than the tools provided in Intel® Parallel Studio XE .  In this short webinar we demonstrate how to use the Hot Spot performance analysis in Intel® VTune™ Amplifier XE  to quickly find your application hot spots.  Knowing where the hot spots are in your code allows you to use the explicit vector programming features in Intel® C++ Composer XE to boost performance of these code sections.  Join one of Intel's knowledgeable support engineers as we demonstrate how a small time investment can yield big returns in application performance.

Two Sessions:

Intel® Xeon® Processors & Intel® Xeon Phi™ Coprocessors - Introduction to High Performance Application Development for Multicore and Manycore-Live

Sept 24 (6:45 A.M. PDT) & Sept 25 (7:00 A.M. PDT)

Sept 24 (6:45 A.M. PDT) & Sept 25 (7:00 A.M. PDT)

Presenters:
Technical Consulting Engineering Team

View Archive

This two day webinar series introduces you to the world of multicore and manycore computing with Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors. Expert technical teams at Intel discuss development tools, programming models, vectorization, and execution models that will get your development efforts powered up to get the best out of your applications and platforms.

Powering up your Fortran Applications in the Neo-heterogenous World with Intel® Xeon Processors & Intel® Xeon Phi™ Coprocessors on Linux and Windows*

Sept 18 9:00 A.M. Pacific

Presenter:
Ron Green

View Archive

The Intel® Xeon Phi™ Coprocessor offers Intel® Fortran Composer XE programmers the opportunity to power up existing Fortran applications. This webinar will focus only on Fortran and the Intel® Xeon Phi coprocessor. This webinar is ideal for the experienced Fortran developers who have not tried the Intel Xeon Phi coprocessor but want to see what it will take to modify their existing Fortran applications to take advantage of it. Some existing knowledge of vectorization, memory alignment, and OpenMP* is helpful but not necessary. Coarray Fortran will not be covered in this webinar. Join us as our technical experts discuss the Fortran programming models, vectorization, and execution models that will get your development efforts powered up to get the best out of the Intel® Xeon Phi™ Coprocessor.

Announcing Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New

Sept 17 9:00 A.M. Pacific

Presenters:
AnnaLee Embry/Gergana Slavova

View Archive

Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance!

For more complete information about compiler optimizations, see our Optimization Notice.
Tags: