Freelance Software Performance Consultant
Tim arrived at Intel® in time for the push for adoption of Itanium and the last ditch effort to overcome mismatch between existing software and the new Pentium® 4 platform, both of which needed to overcome obstacles to vector pipelining and multi-threading. Major HPC applications already took advantage of vectorization and threading on platforms existing prior to Intel’s interest in those modes, but didn’t automatically port effectively to Intel nor AMD* platforms.
Tim’s experience working with developers showed that maintaining a single source code base and relying on compilers to work reliably and optimize for specific targets remained the best tactic. Tim worked for several years on MIC projects prior to retiring from Intel. It remains to be seen whether the marketers can work the requirements of MIC in under the heading of code modernization (better described as high performance programming or supporting multiple level parallelism, if that is what is meant).
Tim worked for several years on the MIC project with NASA* Ames (overflow CFD, et al.), Ohio Supercomputer and mvapich team, and TACC Stampede*. Tim worked on some benchmarks which TACC had committed under NSF contract, which required MPI/OpenMP hybrid to approach optimum coprocessor performance, although OpenMP scaling was limited and probably not valuable on host CPUs.
As an example, Tim has been updating the legacy netlib vector benchmarks at github. These help to show how vectorization and parallelization can be accomplished with Intel and gnu compilers with minimum of changes among compilers and targets.
Recent webinar: vector parallel code
Other Intel Developer Zone publications