Native and Offload Programming Models
This chapter details the various programming models available on the Intel® MIC Architecture. These include the Native programming model, the Heterogeneous Offload model, and the Cilk_Offoad model. Because of the high overhead associated with data movement to/from the Intel® Xeon Phi™ coprocessor, this chapter also covers concepts in data movement and transfer and how to manage data offload.
Note that OpenMP 4.0 includes new directives for offloading execution to attached devices. The Intel Compiler supports the following OpenMP 4.0 features in the latest releases:
- OpenMP 4.0 Features in Intel Fortran Composer XE 2013
- OpenMP 4.0 Features in Intel C++ Composer XE 2013
- Updated Support for OpenMP* 4.0 Features Added in Composer XE 2013 SP1 (C++ and Fortran)
- OpenMP* 4.0 Features in Intel Compiler 15.0
It is important to understand the three programming models (Native, Offload, Cilk_Offload) for the Intel® Xeon Phi™ coprocessor to determine which is the best match for your application. As part of this understanding and analysis, you need to understand the overheads associated with data movement and how to avoid unnecessary data movement and how to get peak transfer rates.
Goals for this chapter are to explore the offload models and data movement topics to determine which may be useful for your application:
The Native Programming Model, covers compiling applications to run directly on the coprocessor
The Heterogeneous Offload Programming Model, covers running a main host program and offloading work to the coprocessor. There are two topics covered in this chapter, standard heterogeneous offload programming model and the Cilk_Offload model.
- Introduction to Asynchronous Offload (C++ and Fortran)
- Cross-Compilation Challenges
It is essential that you read this guide from start to finish using the built-in hyperlinks to guide you along a path to a successful port and tuning of your application(s) on Intel® Xeon Phi™ coprocessors. The paths provided in this guide reflect the steps necessary to get best possible application performance.
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