Intel® Cluster Ready Partner Newsletter Q4 2011 - Feature Stories

Must See Demonstrations at SC11!

I hope you’ll be at SC11 in Seattle this year, because we’ve got a number of demonstrations you really shouldn’t miss. Intel is dedicated to fueling the relentless pursuit of compute capacity that drives the HPC community, and we have innovations to show you that will ultimately help take performance from petaflops to exaflops.

You’ll see advancements that impact every part of the HPC solution stack, including software development, silicon, boards, communications, and more, all designed to support the Intel® Cluster Ready architecture to enable simpler, faster design, testing, implementation, management, and use.

A key focus of several demonstrations will be the future Intel® Xeon® processor E5 family, code-named Sandy Bridge EP. With more cores, more bandwidth, and new vector instructions, Sandy Bridge EP delivers an approximate doubling of floating-point operations per second (FLOPS) that will drive another major leap in HPC application performance. We’ve been working closely with vendors, so complete cluster solutions will be market-ready at launch. You’ll be able to see some of the practical results of that work at SC11, with powerful Intel Cluster Ready certified systems running some of today’s most popular HPC applications.

Looking toward a somewhat longer event horizon, you’ll see how rapidly we’re moving toward exaflop computing performance. Progress is coming on two complementary fronts, and it’s coming faster than Moore’s Law, which has been our benchmark for performance scaling over the past few decades.

The key to this progress is massive parallelism. The 10 hyper-threaded cores in Sandy Bridge EP offer a high-value leap forward in the very near future. Farther down the road, we are on track to shatter that level of parallelism with Intel® Many Integrated Core (Intel® MIC) architecture. We believe these processors will be true game-changers. Total performance capacity will sky-rocket for optimized applications, and cost and energy consumption per FLOP will go way down.

Of course, the catch in that last sentence is the phrase “optimized applications.” Fortunately, it’s not nearly as much of a catch as you might think. You’ll not only see Intel MIC architecture in action at SC11, but also the next generation of Intel software development tools that will help developers take advantage of all that parallelism without reinventing their craft. These comprehensive, easy-to-use software development suites will help developers optimize their code so it will scale effortlessly as parallelism explodes from Sandy Bridge EP to Intel MIC and beyond. Our goal is to deliver lasting value with minimal effort, and I think you’ll be impressed at how far we’ve progressed.

If you’re coming to SC11, pay us a visit, check out our demonstrations, and let’s talk. A few of the demonstrations are mind-blowing. Others are only impressive. Altogether, they provide a look at the Intel technology roadmap for HPC that will help you plan and prepare more effectively. Here’s a quick rundown of what you’ll see.

Demonstration 1: Intel® Cluster Ready

  • What You’ll See: An Intel Cluster Ready certified cluster from Silicon Mechanics based on Sandy Bridge EP, QDR InfiniBand*, and the Red Hat Linux 5.7 operating system. In this multi-vendor demonstration, we’ll be running the latest releases of Flow Science Flow 3D. We’ll also be showcasing cluster provisioning and management solutions from Bright Computing, along with the new Intel® Cluster Checker 1.8 (ready for Sandy Bridge) for simplified cluster testing and validation.

  • Why You Should See It: More than a hundred registered HPC applications are ready to run out of the box on any Intel Cluster Ready certified platform from more than 100 vendors. Come see what that means from a practical standpoint. This is the state-of-the-art for simple, affordable cluster computing, and an opportunity to see the potential value for you and your customers.

Demonstration 2: Scaling MPI to Increase Cluster Performance

  • What You’ll See: As the number of cores per node increases, so do the challenges for MPI developers. Come see the “ultimate HPC development suite” from Intel. We’ll show you how these next-generation tools enable developers to simultaneously optimize MPI and threading parallelism to deliver superior parallel throughput at every level, all the way from a single processor to an entire cluster. We’ll also showcase the performance benefits, with a demonstration showing 4-6X faster performance for finite element analysis (FEA) using LS-Dyna.
  • Why You Should See It: This demonstration will give you an inside look at powerful, next-generation Intel software development tools. It is a must-see demonstration for any developer interested in breaking through current and future HPC performance barriers.

Demonstration 3: Next-Generation Software Tools for Threaded Parallelism

  • What You’ll See: Three visually stunning demonstrations highlight the performance benefits of parallelized code running on a Sandy Bridge EP-based platform with Intel Advanced Vector Extensions (Intel AVX). Three different programming models are showcased. All three are powerful and easy to implement using Intel tools, software component, and libraries. We’ll also be showcasing cluster provisioning and management solutions from Platform Computing!
  • Why You Should See It: These demonstrations highlight real math and real code applied to a variety of fluid flow simulations running on a market-ready HPC platform-with compelling impact. You have to see it to believe it.

Demonstration 4: ANSYS Mechanical–Simulation of Touchscreen

  • What You’ll See: ANSYS Mechanical provides a nonlinear structural analysis of a hand using excessive force when drawing on a Touchscreen. The material experiences plasticity, while the hand is modeled as a rigid body.
  • Why You Should See It: You’ll learn how ANSYS speeds up the simulation by implementing Intel® AVX instructions, which increase the floating point performance of the future Intel® Xeon® processor E5 family (Sandy Bridge EP).

Demonstration 5: EPSD Boards and Systems based on Sandy Bridge EP.

  • What You’ll See: You’ll get an up-close look at the latest boards, chassis and systems building blocks from Intel, including what one customer called, “The best HPC server board in the industry.” Our expanded product offerings based on Sandy Bridge EP highlight the advantages of increased memory and I/O bandwidth and superior I/O flexibility. Purposely built for the HPC segment, they are capable of running the most demanding high performance computing applications on the planet and delivering the compute density and performance/watt required to power multiple clusters in the TOP500.
  • Why You Should See It: You're on the cutting edge of science, and business. Trust Intel® Server Products to deliver the performance you need to solve tomorrow's problems.
For more complete information about compiler optimizations, see our Optimization Notice.