Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2, AVX-512) and processor-specific optimizations

 

What are the IA-32 and Intel® 64 processor targeting options in the Intel® compilers?
There are three main types of processor-specific optimization options:

  1. Processor-specific options of the form /arch:<code> on Windows* ( -m<code> on Linux* or Mac OS* X) generate specialized code for processors specified by <code>. The resulting executables from these processor-specific options can be run on the specified or later Intel® and compatible, non-Intel® processors that support the instruction set. The executable may incorporate optimizations specific to those processors and use a specific version of the Intel® Streaming SIMD Extensions (Intel® SSE) instruction set and/or the Intel® Advanced Vector Extensions (Intel® AVX) instruction set; on older processors without support for the corresponding instruction set, an illegal instruction or similar error may occur.

    The value for <code> can be one of the following (note that <code> must be lower case on Linux or OS X, but may be either case on Windows) :

     

    core-avx2  May generate Intel® AVX2, AVX, Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions. /arch:core-avx2 is supported on Windows* but -mcore-avx2 is not supported for Linux* or OS X* (use -march=core-avx2 instead).
    avxMay generate Intel® AVX, Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions.
    sse4.2May generate Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions.
    sse4.1May generate Intel® SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions.
    ssse3May generate SSSE3, Intel® SSE3, SSE2 and SSE instructions.
    sse3May generate Intel® SSE3, SSE2 and SSE instructions.
    sse2May generate Intel® SSE2 and SSE instructions. /arch:SSE2 is the default on Windows and -msse2 is the default on Linux.
    ia32Generates generic IA-32 compatible code. Can only be used with the /arch: or -m switches. (IA-32 compiler only).

     

  2. Processor-specific options of the form /Qx<code> on Windows*( -x<code> on Linux* or OS X*) generate specialized code for processors specified by <code>. The resulting executables from these processor-specific options can only be run on the specified or later Intel® processors, as they incorporate optimizations specific to those processors and use a specific version of the Intel Streaming SIMD Extensions (Intel SSE) instruction set and/or the Intel® Advanced Vector Extensions (Intel® AVX) instruction set. This switch enables some optimizations not enabled with the corresponding switches /arch:x<code> or -m<code>. A run-time check is inserted in the resulting executable that will halt the application if run on an incompatible processor. This is intended to help you quickly find out that the program was not intended for the processor it is running on and potentially avoids an illegal instruction error. For this check to be effective, the source file containing the main program or the dynamic library main function should be compiled with this option enabled.

    The value for <code> can be (in upper or lower case):

     

    COMMON-AVX512May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for future Intel® processors. Available in compiler version 15 update 2 and later.
    MIC-AVX512May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Prefetch instructions, Intel® AVX-512 Exponential and Reciprocal instructions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3SSE3SSE2 and SSE instructions for Intel® processors. Optimizes for the Intel® Xeon Phi processor x200 product family. Available in compiler version 14 update 1 and later.
    CORE-AVX512May generate Intel® AVX-512 Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-512 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
    CORE-AVX2May generate Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for 4th, 5th and 6th generation Intel® Core™ processors and the Intel® Xeon® Processor E3 v3, E5 v3, E7 v3, E3 v4, E5 v4 and E7 v4 families. Available in compiler versions 13 and later.
    CORE-AVX-IMay generate Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors, including instructions for 3rd generation Intel® Core™ processors. Optimizes for 3rd generation Intel® Core™ processors and the Intel® Xeon® Processor E3 v2, E5 v2 and E7 v2 families.
    AVXMay generate Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for 2nd generation Intel® Core™ i7, i5 and i3 processor families and the Intel® Xeon® Processor E5 and E3 families.
    SSE4.2May generate Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for the previous generation Intel® Core™ i7, i5 and i3 processor families, the Intel® Xeon® 55XX, 56XX and 75XX series and the Intel® Xeon® Processor E7 Family.
    ATOM_SSE4.2May generate Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. May also generate MOVBE instructions if the option /Qinstruction:movbe (-minstruction=movbe) is set. Optimizes for Intel® Atom™ processors that support Intel® SSE4.2 and MOVBE instructions.
    SSE4.1May generate Intel® SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for the 45nm Hi-k next generation Intel® Core™ processors.
    SSSE3May generate Intel® SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for Intel® Core™ microarchitecture. -xssse3 is the default for the Intel® 64 architecture compiler on OS X*.
    ATOM_SSSE3May generate SSSE3, Intel® SSE3, SSE2 and SSE instructions for Intel® processors. May also generate MOVBE instructions if the option /Qinstruction:movbe (-minstruction=movbe) is set. Optimizes for Intel® Atom™ processors that support SSSE3 and MOVBE instructions.
    SSE3May generate Intel® SSE3, SSE2 and SSE instructions. Optimizes for the enhanced Intel® Pentium® M processor microarchitecture and Intel® Netburst microarchitecture. -xsse3 is the default for the IA-32 compiler on OS X*.
    SSE2 May generate Intel® SSE2 and SSE instructions. Optimizes for the Intel® Netburst microarchitecture.
    HOSTMay generate instructions from any of the above instruction sets that are supported by the compilation host processor. See the Intel® Compiler User and Reference Guide for further information, including behavior on compatible, non-Intel processors.

     

  3. Processor-dispatch options of the form /Qax<code> on Windows* ( -ax<code> on Linux* or OS X*) allow the generation of multiple code paths for Intel® processors. Processor dispatch technology performs a check at execution time to determine which processor the application is running on and use the most suitable code path for that processor. Compatible, non-Intel processors will take the default optimized code path. The switches described in 1. and 2. above can be used to modify the default optimized code path.

    You can use two of the feature values by combining them. For example, you can specify -axSSE4.1,SSSE3 (Linux OS and OS X) or /QaxSSE4.1,SSSE3 (Windows OS). In this example, an Intel® SSE4.1-optimized sequence will be used on Intel processors that support it, an Intel® SSSE3-optimized sequence on Intel processors that support SSSE3 but not SSE4.1, and a default path on all other processors.

    Where the value for <code> can be:

     

    COMMON-AVX512May generate Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3SSE3SSE2 and SSE instructions for Intel® processors. Optimizes for future Intel® processors. Available in compiler version 15 update 2 and later.
    MIC-AVX512May generate Intel® AVX-512 Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Prefetch instructions, Intel® AVX-512 Exponential and Reciprocal instructions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3SSE3SSE2 and SSE instructions for Intel® processors. Optimizes for the Intel® Xeon Phi processor x200 product family. Available in compiler version 14 update 1 and later.
    CORE-AVX512May generate Intel® AVX-512 Foundation instructions, Intel® AVX-512 Conflict Detection instructions, Intel® AVX-512 Doubleword and Quadword instructions, Intel® AVX-512 Byte and Word instructions, Intel® AVX-512 Vector Length extensions, Intel® AVX2, AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for a future Intel® processor. Available in compiler version 15 update 1 and later.
    CORE-AVX2 May generate Intel® AVX2, Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Available in compiler versions 13 and later.
    CORE-AVX-IMay generate Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors, including instructions for 3rd generation Intel® Core™ processors.
    AVXMay generate Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors.
    SSE4.2May generate Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors.
    SSE4.1May generate Intel® SSE4.1,SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors.
    SSSE3May generate Intel® SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors.
    SSE3May generate Intel® SSE3, SSE2 and SSE instructions for Intel® processors.
    SSE2 May generate Intel® SSE2 and SSE instructions for Intel® processors.
 

Which processor-specific option is best for my processor?

COMMON-AVX512A future Intel® Processor. 
MIC-AVX512The Intel® Xeon Phi processor x200 product family.
CORE-AVX512A future Intel® Processor
CORE-AVX2

4th Generation Intel® Core™ Processors
5th Generation Intel® Core™ Processors
6th Generation Intel® Core™ Processors
7th Generation Intel® Core™ Processors
Intel® Xeon® Processor E7 v3 Family
Intel® Xeon® Processor E5 v3 Family
Intel® Xeon® Processor E3 v3 Family
Intel® Xeon® Processor E7 v4 Family
Intel® Xeon® Processor E5 v4 Family
Intel® Xeon® Processor E3 v4 Family

CORE-AVX-I3rd Generation Intel® Core™ i7 Processors
3rd Generation Intel® Core™ i5 Processors
3rd Generation Intel® Core™ i3 Processors
Intel® Xeon® Processor E7 v2 Family
Intel® Xeon® Processor E5 v2 Family
Intel® Xeon® Processor E3 v2 Family
AVX2nd Generation Intel® Core™ i7 Processors
2nd Generation Intel® Core™ i5 Processors
2nd Generation Intel® Core™ i3 Processors
Intel® Xeon® Processor E5 Family
Intel® Xeon® Processor E3 Family
SSE4.2Previous Generation Intel® Core™ i7 Processors
Previous Generation Intel® Core™ i5 Processors
Previous Generation Intel® Core™ i3 Processors
Intel® Xeon® 55XX series
Intel® Xeon® 56XX series
Intel® Xeon® 75XX series
Intel® Xeon® Processor E7 Family
ATOM_SSE4.2Intel® Atom™ processors that support Intel® SSE4.2 instructions.
SSE4.1Intel® Xeon® 74XX series
Quad-Core Intel® Xeon 54XX, 33XX series
Dual-Core Intel® Xeon 52XX, 31XX series
Intel® Core™ 2 Extreme 9XXX series
Intel® Core™ 2 Quad 9XXX series
Intel® Core™ 2 Duo 8XXX series
Intel® Core™ 2 Duo E7200
SSSE3Quad-Core Intel® Xeon® 73XX, 53XX, 32XX series
Dual-Core Intel® Xeon® 72XX, 53XX, 51XX, 30XX series
Intel® Core™ 2 Extreme 7XXX, 6XXX series
Intel® Core™ 2 Quad 6XXX series
Intel® Core™ 2 Duo 7XXX (except E7200), 6XXX, 5XXX, 4XXX series
Intel® Core™ 2 Solo 2XXX series
Intel® Pentium® dual-core processor E2XXX, T23XX series
ATOM_SSSE3Intel® Atom™ processors
SSE3Dual-Core Intel® Xeon® 70XX, 71XX, 50XX Series
Dual-Core Intel® Xeon® processor (ULV and LV) 1.66, 2.0, 2.16
Dual-Core Intel® Xeon® 2.8
Intel® Xeon® processors with SSE3 instruction set support
Intel® Core™ Duo
Intel® Core™ Solo
Intel® Pentium® dual-core processor T21XX, T20XX series
Intel® Pentium® processor Extreme Edition
Intel® Pentium® D
Intel® Pentium® 4 processors with SSE3 instruction set support
SSE2Intel® Xeon® processors
Intel® Pentium® 4 processors
Intel® Pentium® M
IA32Intel® Pentium® III Processor
Intel® Pentium® II Processor
Intel® Pentium® Processor

 

 

Which processor is targeted by default?

  • When compiling for the IA-32 architecture or the Intel® 64 architecture on Windows* or Linux*, /arch:SSE2 (Windows*) or -msse2 (Linux*) is the default. The resulting code path should run on the Intel Pentium 4 and Intel Xeon processors with SSE2 support and other later Intel processors or compatible non-Intel processors with SSE2 support.
  • When compiling for the IA-32 architecture on OS X*, -xSSE3 is the default. The compiler may generate SSE3, SSE2 and SSE instructions and the code is optimized for enhanced Pentium M processor microarchitecture.
  • When compiling for the Intel® 64 architecture on OS X* , -xSSSE3 is the default. The compiler may generate SSSE3, SSE3, SSE2 and SSE instructions and the code is optimized for the Intel® Core™ microarchitecture.

To target older IA-32 systems without support for SSE2 instructions, such as systems based on the Intel® Pentium® III Processor, use the switch /arch:ia32 (Windows*) or -mia32 (Linux*).

For information about other, older processor targeting options and their relation to the recommended options above, see
http://software.intel.com/en-us/articles/ia-32-and-intel-64-processor-targeting-overview

Other common questions (continuation article)

For more complete information about compiler optimizations, see our Optimization Notice.

5 comments

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anonymous's picture

I am getting trouble with this error: "SSE instruction set not enabled"

how I can figure this out? I have ACER i7, Ubuntu 11.10, please any one can help me?

running:
sudo cat /proc/cpuinfo | grep flags
gives:

flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx rdtscp lm constant_tsc arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 x2apic popcnt xsave avx lahf_lm ida arat epb xsaveopt pln pts dts tpr_shadow vnmi flexpriority ept vpid

any help will be appreciated!

anonymous's picture

I am getting trouble with this error: "SSE instruction set not enabled"

how I can figure this out? I have ACER i7, Ubuntu 11.10, please any one can help me?

running:
sudo cat /proc/cpuinfo | grep flags
gives:

flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx rdtscp lm constant_tsc arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 x2apic popcnt xsave avx lahf_lm ida arat epb xsaveopt pln pts dts tpr_shadow vnmi flexpriority ept vpid

any help will be appreciated!

anonymous's picture

Thank you for that,

I have probem:
error: #error "SSE instruction set not enabled"
how I can enable any option of them (-msse2,msse4.2, etc)? plz in detaled!
e
any help will be appreciated!

anonymous's picture

for Intel Core 2 only 45nm processors will only have SSE4.1 for 65nm only have up to SSSE3

anonymous's picture

And what about -xHost option? Can we use this flag to auto-detect the best option for a host processor?

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