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Processing Arrays of Bits with Intel® Advanced Vector Extensions 2 (Intel® AVX2)

It is only a few weeks until you will get a chance to get your hands on the 4th Generation Intel® Core&tm; Processor Family formerly code-named Haswell. This architecture will come with some very nice features including Intel® Advanced Vector Extensions 2 (Intel® AVX2). Most notably, Intel®

Measuring performance in HPC

This is the first article in a series of articles about High Performance Computing with the Intel Xeon Phi. The Intel Xeon Phi is the first commercial product of Intel to incorporate the Many Integrated Core architecture. In this article I will present the basics of the Xeon Phi architecture, the programming models and what we can do to measure the performance in cycles for micro benchmarks.

  • Professors
  • Students
  • Linux*
  • C/C++
  • Intermediate
  • Intel® C++ Compiler
  • Intel® C++ Compiler and Performance Library for QNX* Neutrino* RTOS
  • Intel® Cilk™ Plus
  • Intel® Math Kernel Library
  • Intel® Parallel Studio XE Composer Edition
  • OpenMP*
  • performance
  • timing
  • offload
  • native
  • Debugging
  • Intel® Many Integrated Core Architecture
  • Optimization
  • Parallel Computing
  • Threading
  • Vectorization
  • Code Examples from Intel® Xeon Phi™ Coprocessor Book

    The code used in examples (Chapters 2-4) in our book Intel® Xeon Phi™ Coprocessor High Performance Programming can be downloaded from the book's website. We appreciate attribution, but there are no restrictions on use of the code - please use and enjoy! You can use the step by step instructions in the book or if you prefer we've included a Makefile for each of the chapter examples to make life a little easier.

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