Product Support

Serial Peripheral Interface Specifications

A 25-MHz SPI bus (SPI_1) is available on the J6 connector with three slave selects and another 25-MHz SPI bus (SPI_0) with two slave selects on the J7 connector. The bus speed is 25 MHz in master mode and 16.67 MHz in slave mode. In a single-frame transfer, the SoC supports all four possible combinations for the serial clock phase and polarity. In multiple frame transfer, the Intel® Joule™ module supports only a clock phase setting of 1.

Booting the Development Platform

My USB device won’t show up at all in BIOS

Try using a different USB device, port, or USB hub.

My development platform won’t boot from a USB drive or microSD* card

First, make sure that your microSD card or USB device is securely connected to the development platform. Also make sure you don't have a microSD card and a USB drive plugged into the development platform at the same time.

Face Detection

Overview

A very simple test application is provided to demonstrate the face detection functionality of the Photography Vision Library and the utilization of the example Gstreamer filter pvl_face_detection.

Example

Start it with the command:

CVTraceGUI

When the GUI appears click on "video_file” and then on “camera”.

Default BIOS Pinmapping

Pinmapping for the breakout connectors can be found in Module Board-to-Board Connector Pinout. The tables below provides the pin assignment, signal name, and description for the signals on the breakout connectors J12 and J13. The default breakout usage refers to the vantage point of the expansion board. For example, the SPI_1_MISO_LS signal originates in the breakout board and is delivered to the expansion board, therefore it is an input.

Hardware Block Diagram

The compute module interfaces to the expansion board through twin 100-pin connectors; these connectors are referenced as J2 and J3 on the module and J12 and J13 on the expansion board, respectively.

These module connectors are abstracted to a black-box of the module in the diagram found in Expansion Board Block Diagram. This is done to keep focus on the expansion board physical interfaces.

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