C-states and P-states are very different

C-states are idle states and P-states are operational states. This difference, though obvious once you know, can be initially confusing.

With the exception of C0, where the CPU is active and busy doing something, a C-state is an idle state. Since an idle CPU isn't doing anything (i.e. any useful work), why not shut it down? No one is going to notice since there's no one using it. (Letting a CPU run at full bore when idle is like driving in circles very fast; all you're doing is going nowhere quickly.)

A P-state is an operational state, meaning that the core / processor can be doing useful work in any P-state. The most obvious example is when your laptop is using a low power profile and operating on battery. The OS will lower the C0 operating frequency and voltage, i.e. enter a higher P-state. Reducing the operating frequency reduces the speed at which the processor operates, and so the energy usage per second (i.e. power). Reducing the voltage decreases the leakage current from the CPU's transistors, making the processor more energy efficient resulting in further gains. The net result is a significant reduction in the energy usage per second of the processor. On the flip side, an application will take longer to run. This may or may not be a problem from a power perspective. I'll talk about this issue in some depth in a later blog.

C-states and P-states are also orthogonal. This is a fancy mathematical term meaning that each can vary independently of the other. This doesn't mean that in the higher C-states, the voltage doesn't change. It only means that when you resume C0, you go back to the operating frequency and voltage defined by that P-state.

Next time: C-states, C-states and even more C-states

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Hi Alex,

General mechanisms (what it is) are often publicly available. Specifics (how we got the silly thing to work) are usually not.

Unless your university / company have applicable non-disclosure agreements in place, I can't go into more specifics.


Hello, Taylor.
I am interested in the exact details of transitioning from a P0 state to a P1 state (for example, also viceversa) on a current multi-core Intel processor:
- how many microseconds does it take
- what happens during the transition (the freq remains the same as for P0)
- is there any extra energy cost consumed.

Could you please at least point me to the right literature for this (I only found these papers: http://download.intel.com/technology/itj/2006/volume10issue02/vol10_art03.pdf and http://download.intel.com/technology/itj/2003/volume07issue02/art03_pentiumm/vol7iss2_art03.pdf ). You mentioned about some power management patents - could you please point me to them.

Thank you,
Alex Susu

Hi Joe,

By entering a P-state, I mean that the processor goes from one voltage, frequency pair to another. So my portable going from P0 to P1 means that the start state is (2333.0 MHz, Va) and the final state is (979.9 MHz, Vb), where Va>Vb.

An interesting detail is how the processor moves from P0 to P1. It doesn't move in one big step but in increments. Remember, the processor has to stay operational, meaning that it must produce correct results. Intelligently moving in small steps is going to let us do this more easily.

As to your question about P-states existing only in C0, the answer that this is generally the case. Hmmm, "generally." This leaves alot to the imagination, doesn't it. I'll talk about this in a more formal article. Yes, I haven't completely dropped this blog. I've been really really busy (aren't we all). I should have a little more time given Q2 is over.

Now some of you might wonder if I'm revealing any Intel proprietary info. I work very hard to insure that I do not. Here's one technique that I use to make sure: I skim the Intel patents. If it's in a patent, it's publically available.

If any of you are really interested in the details some of what I talk about, and can manage to stay awake, take a look at power management patents.


i like it. can you elaborate on what it means to enter a p-state? with the exception of c0, p-states do not exist in the idle c-states; correct?


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