A Meetup for Bay Area Parallel/Multicore Programmers 3/24/11


Exclusive Invitation
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You are invited to attend the first Intel® Parallel Programming MeetUp at Intel HQ in Santa Clara, CA on Thursday, March 24. Register now to attend.The Parallel Programming MeetUp is for software developers in the San Francisco Bay Area to learn about Intel’s 2nd Generation Intel® Core™ Processor Family (Codename Sandy Bridge), and how to gain industry recognition by becoming an author for the Intel Parallel Programming Community.Doors open at 3:00 pm with demos and technical experts available to meet. Special 2nd Generation Intel® Core™ Processor Family (Codename Sandy Bridgeand) and Intel® AVX presentations will be made at 4:00 pm and again at 6:00 pm. Refreshments will be provided.  


Learn about 2nd Generation Intel® Core™ Processor Family (Codename Sandy Bridge) and parallel programming. Presentation times: 4:00pm and 6:00pm (Meetup Duration: 3pm – 7pm PST)

 See developer tool demos of the Intel® Parallel Studio, Intel® AVX, and Intel® Concurrency Checker 

 Refreshments will be served 

 Learn about the Parallel Programming Community, how to be an active author and what this can do for you 

 Meet the Parallel Programming Community Manager, Intel® Software Partner Program managers and other developers 

 Provide feedback to the Parallel Programming Community on 2nd Generation Intel® Core™ Processor Family (Codename Sandy Bridge) 

Please register in advance on the Intel® Learning Network registration site using your Intel® Software Network user name and password. If you don’t have an Intel Software Network user name, you may register for an Intel Learning Network user name and password so that you can register for the Meetup 



Register Now

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1 comment

Art Scott's picture

Parallel geometric algorithms for multi-core computers[PDF] from inria.fr
VHF Batista, DL Millman, S Pion… - Computational Geometry, 2010 - Elsevier
Computers with multiple processor cores using shared memory are now ubiquitous. In this
paper, we present several parallel geometric algorithms that specifically target this
environment, with the goal of exploiting the additional computing power. The algorithms ...
Cited by 6 - Related articles - All 12 versions

“...introduce as a foundational element the design of a container
data structure that both provides concurrent addition and removal operations and is com-
pact in memory. ...
“The relevance of these algorithms in practice depends not only on their
implementability, but also on the hardware architecture targeted.”
Moreover, given the high difficulty of properly benchmarking such complex implementations
from all interesting angles, it could be a good idea to organize some friendly competition
around the theme of parallel Delaunay triangulations at some point.”

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