Quick chat about MIC architecture with Mike Dewar, NAG

I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. - a company Intel has had the good fortune to work with for years.

NAG is one of a handful of companies that have been providing feedback on Knights Ferry (prototype MIC architecture).

Mike told me: "We found porting existing routines from the NAG Library to the Intel Many Integrated Core Architecture (MIC) to be a relatively quick and painless process. The team was impressed at the way Intel has extended their existing software tools to support the MIC environment, allowing them to work in a familiar and productive environment."

I quizzed Mike on what it took to get it running on Knights Ferry, and he did share the one type of tuning they have to explore. They use OpenMP*, which has generally meant that the number of threads is more like 10-20 instead of the 120 threads they use on Knights Ferry.  I'll have to write more about that later - scaling and vectorization are keys as multicore and many-core grow. No mystery there. The good news is that their use of OpenMP made this a straightforward challenge they understood. It was not a mystery to them. They also make good use of Intel® MKL in their library as well, and of course Intel supports that for MIC architecture.

It is great to know that NAG users will have the opportunity to continue using NAG software with Knights Corner.

 

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James R.'s picture

NAG posted more information at http://www.nag.co.uk/Market/articles/nag_participating_with_intel_mic.pdf

James R.'s picture

MIC = Many Integrated Core, an architecture demonstrated by Intel for integrating very high number of cores in a single product. The prototype (Knights Ferry) has 30-32 cores, the produce (Knight Corner - due out on 22nm in the future, first silicon demoed in Nov 2011 at SC11) has more than 50 cores.

anonymous's picture

MIC stands for...?

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