ispc: Intel® Xeon® and Intel® Xeon Phi™ support now

Vectorization is an industry wide challenge - and if you are interested in seeing some one of the industry leading exploration projects (and trying it on your code)... then you may want to look at ispc.

ispc is an R&D compiler for a C-based language that is targeted for exploring the performance available from doing SPMD (single program, multiple data) computation on SIMD units found on CPUs and on Intel® Xeon Phi™ coprocessors (using the Intel Many Integrated Core (MIC) architecture).  It has delivered performance competitive with hand-coded SSE and AVX for a variety of graphics and throughput kernels and typically delivers a 3x-4x speedup versus scalar C/C++ code on SSE and 5-7x speedup on AVX (for computations that are amenable to SPMD implementation), while still providing the ease-of-use of a C-like language.

The paper "ispc: A SPMD Compiler for High-Performance CPU Programming" by Matt Pharr and Bill Marks won "best paper award" at InPar 2012. It is an excellent paper that articulates the challenges of vectorization and explains the important context very well. It also advances a solid demonstration of what is possible when you think about SPMD on SIMD models clearly. For particular note is the approach of quantifying the effects of turning off individual proposed extensions (uniform, coherent control flow). Fundamental and key concepts like AOS vs. SOA are well explained (with drawings). I think everyone should understand how wider vectors (CPU and GPU) interact with programming languages and will shape programming for the next several decades… and everyone should read this paper in its entirety at least once.

ispc is available as an open source project from Support for Intel Xeon Phi is now available in the public ispc release.  Read the instructions at after downloading.

The paper and talk can be downloaded from Matt Pharr and William R. Mark, ispc: A SPMD Compiler for High-Performance CPU Programming, Proc. InPar 2012. Best Paper Award. (Talk slides).

For more complete information about compiler optimizations, see our Optimization Notice.


anonymous's picture

ISPC also supports ARM now.

R Lloyd Rankin's picture

The need to extract maximum value from vector units and ops is certainly of great importance when general purpose CPUs are used. I'm reminded of the late Seymour Cray saying "If you want to plow a field, do you want the plow pulled by two bulls or 1024 chickens?" This was in the time of supercomputing based on massive vector processors and before Cray, Inc. started making big "hen house" machines. There is a question to be addressed as to whether it is more efficient to do SPMD on large numbers of simpler cores or attempt to attack parallel processing both from the vector capabilities within each core and from the mass of cores simultaneously. This approach does further complicate the heterogeneous massively parallel coding issue. The early stages of Xeon Phi algorithm design will be fascinating to follow. I'll be interested in looking at the project code too. Sure wish I had a Xeon Phi board to tinker with.

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