Documentation for uncore performance monitoring units

Hello everyone,

The uncore performance monitoring units (uncore PMUs) provide many useful information like memory controller traffic, traffic between sockets/processor packages, energy related metrics in the uncore (sleep states for Intel® Quick Path Interconnect links or DRAM sleep states for example). These metrics can be used in tools for system and platform analysis.

The documentation for uncore performance monitoring units for various Intel processors is distributed over different documents. In this blog I will try to summarize the links to the corresponding documents that should help searching for the correct document.

Processor Codename Document
Intel® Core™ various memory traffic, last level cache (CBO) events in SDM (chapter 18 Performance Monitoring)
Intel® Xeon® 5500 and 5600 series  Nehalem-EP and Westmere-EP SDM (Chapter 18 Performance Monitoring, Sections 18.7.2 and 18.8 accordingly) and this guide
Intel® Xeon® 7500 series  Nehalem-EX this uncore PMU guide
Intel® Xeon® E5 series  SandyBridge-EP (Ivytown-EP) this uncore PMU guide
Intel® Xeon® E7 series  Westmere-EX this uncore PMU guide
Intel® Xeon® E5 v2 and E7 v2 series  Ivybridge-EP and Ivybridge-EX this uncore PMU guide
Intel® Xeon® E5 and E7 v3 series  Haswell-EP and Haswell-EX this uncore PMU guide
Intel® Xeon® D-1500 series  Broadwell-DE this uncore PMU guide

 

I hope this summary can help you.

 

Best regards,

Roman

For more complete information about compiler optimizations, see our Optimization Notice.