Author's Blogs

Intel Xeon Phi coprocessor support by software tools
By James Reinders (Intel) Posted on 09/20/12 4
A number of tool vendors have announced they will be providing versions of their software tailored to supporting MIC architecture, starting with the Intel Xeon Phi co-processor. Here are the ones I know about and can share (there are more who will make their own announcement in the future): Compi...
VMware Fusion 5 supports Intel® VTune™ Amplifier event sampling
By James Reinders (Intel) Posted on 09/16/12 0
One of the great features in Intel® VTune™ Amplifier is the use of the event monitoring registers built into Intel processors. These can give us important insights into what is really happening on a system. The event monitoring allows the profiling of code in terms of what causes caches misses, u...
Parallel Studio XE 2013 is here
By James Reinders (Intel) Posted on 09/05/12 4
Today we announced Parallel Studio XE 2013 (available immediately) and Cluster Studio XE 2013 (available in Q4 2012). You can learn more about the details in Issue 11 of Parallel Universe Magazine. Issue 11 includes articles on the "top ten new features," the pointer checker feature and condition...
ispc: Xeon and Xeon Phi support now
By James Reinders (Intel) Posted on 07/27/12 2
Vectorization is an industry wide challenge - and if you are interested in seeing some one of the industry leading exploration projects (and trying it on your code)... then may want to look at ispc. ispc is an R&D compiler for a C-based language that is targeted for exploring the performance ...
Knights Corner: Open source software stack
By James Reinders (Intel) Posted on 06/05/12 1
Knights Corner: Open source software stack As mentioned in “Knights Corner micro-architecture support” the open source software stack consists of an embedded Linux, a minimally modified GCC, plus driver software. There is a package for GDB available separately as well. Links for these resources c...
Knights Corner micro-architecture support
By James Reinders (Intel) Posted on 06/05/12 26
How does a high performance SMP on-a-chip sound to you?  I can now share, for the first time, key details about our vision for Knights Corner (the aforementioned high performance SMP on-a-chip), and our thinking behind the software architecture and features.   There is a lot to cover here so I’ll...
TACC symposium and programming two SMP-on-a-chip devices
By James Reinders (Intel) Posted on 04/26/12 0
Real results for many-core processors illustrate the power of a familiar configuration (SMP) even when reduced to a single chip. SMP on-a-chip can use the same applications, same tools, offer the same flexibility and pose familiar challenges that are solved by familiar techniques and skills. I re...
Wellington and Austin: programming lots of cores
By James Reinders (Intel) Posted on 04/03/12 0
A couple of back-to-back opportunities to see great talks about harness lots of cores, and to give talks about programming options and why we do not need to give up on programmability in our quest for high performance.Wellington this week, Austin next week. Programming is not easy, and neither is...
Coarse-grained locks and Transactional Synchronization explained
By James Reinders (Intel) Posted on 02/07/12 3
Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog. In my blog "Transactional Synchronization in Haswell," I describe new instructions (Intel TS...
Transactional Synchronization in Haswell
By James Reinders (Intel) Posted on 02/07/12 12
We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be downloaded. In this blog, I’ll introduce Intel TSX and...