Boost System & IoT Device Application Performance

  • A robust C and C++ compiler to efficiently implement high-level, task-based parallelism, and vectorization for data parallelism
  • Compatible with multiple compilers and portable to many operating systems

Boost the speed of embedded and systems applications by incorporating the Intel® C++ Compiler. It provides industry leading performance while simplifying building code that takes advantage of increasing core count in modern processors. It’s a drop-in addition for C and C++ development and has broad support for current and previous C and C++ standards with full C++11 and most C99 support.

What's New in the 2018 Release

  • Develop optimized and vectorized code for various Intel® architectures, including Intel Atom® and Intel Xeon® processors.
  • Leverage the latest language and OpenMP* standards, which are compatible with leading compilers and IDEs.
  • Conduct virtual function vectorization to boost performance of your object-oriented C++ code.
  • Use the SIMD Data Layout Template (SDLT) library to vectorize your standard C++ array-of-structure code.
  • Analyze and optimize performance with an easy plugin for Intel® VTune™ Amplifier.

benchmark for performance on Linux

Benchmark results were obtained prior to implementation of recent software patches and firmware updates that are intended to address exploits referred to as "Spectre" and "Meltdown." Implementation of these updates may make these results inapplicable to your device or system.

Configuration: Intel® Core™ i5 processor 7600 at 3.50 GHz, 16 GB RAM. Intel® Hyper-Threading Technology is not supported. Software: Intel® C++ Compiler 18.0.1, GNU Compiler Collection (GCC) 7.2.0. Clang (LLVM front end) 5.0. Linux*: Red Hat Enterprise Linux Server* release 7.2 (Maipo), kernel 3.10.0-514.el7.x86_64. SPEC* Benchmark. SmartHeap 10 was used for CXX tests when measuring SPECint* benchmarks.

SPECint_rate_base_2006 (32 bit) compiler switches: SmartHeap 10 was used for C++ tests. Intel® C and Intel C++ Compilers 18.0: '-m32 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C code adds option –static. GCC 7.2.0: '-m32 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. Clang 5.0: '-m32 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops C++ code adds option –fno-fast-math. SPECfp®_rate_base_2006 (64 bit) compiler switches: Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -auto-p32. C code adds option –static. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops SPECint_speed_base_2006 (64 bit) compiler switches: SmartHeap 10 were used for C++ tests. Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -auto-p32. C code adds options –static –parallel. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. C code adds options -ftree-parallelize-loops=4. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops. C++ code adds options -fno-fast-math -fno-fast-math SPECfp_speed_base_2006 (64 bit) compiler switches: Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -static -auto-p32. C code adds option –parallel. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. C code adds option -ftree-parallelize-loops=4. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops.

Benchmark source: Intel Corporation

1See below for further optimization notes and disclaimers.


benchmark for performance on Linux

Benchmark results were obtained prior to implementation of recent software patches and firmware updates that are intended to address exploits referred to as "Spectre" and "Meltdown." Implementation of these updates may make these results inapplicable to your device or system.

Configuration: Intel® Core™ i5 processor 7600 at 3.50 GHz, 16 GB RAM, Intel® Hyper-Threading Technology is not supported. Software: Intel® C++ Compiler 18.0.1, GCC 7.2.0. Clang/LLVM 5.0. Linux: Red Hat Enterprise Linux Server release 7.2 (Maipo), kernel 3.10.0-514.el7.x86_64. SPEC Benchmark. SmartHeap 10 was used for CXX tests when measuring SPECint benchmarks.
SPECint_rate_base_2006 (32-bit) compiler switches: SmartHeap 10 were used for C++ tests. Intel C and Intel C++ Compilers 18.0: '-m32 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 C code adds option –static. GCC 7.2.0: '-m32 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. Clang 5.0: '-m32 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops C++ code adds option –fno-fast-math.

SPECfp_rate_base_2006 (64 bit) compiler switches: Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -qopt-mem-layout-trans=3 -auto-p32. C code adds option –static. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops SPECint_speed_base_2006 (64 bit) compiler switches: SmartHeap 10 were used for C++ tests. Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -auto-p32. C code adds options –static –parallel. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. C code adds options -ftree-parallelize-loops=4. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops. C++ code adds options -fno-fast-math -fno-fast-math. SPECfp _speed_base_2006 (64 bit) compiler switches: Intel C and Intel C++ Compilers 18.0: '-m64 -xCORE-AVX2 -ipo -O3 -no-prec-div -qopt-prefetch -static -auto-p32. C code adds option –parallel. GCC 7.2.0: '-m64 -Ofast -flto -march=core-avx2 -mfpmath=sse -funroll-loops. C code adds option -ftree-parallelize-loops=4. Clang 5.0: '-m64 -Ofast -march=core-avx2 -flto -mfpmath=sse -funroll-loops.

Benchmark source: Intel Corporation

1See below for further optimization notes and disclaimers.


 

benchmark for the Intel Core I 5 processor

Benchmark results were obtained prior to implementation of recent software patches and firmware updates that are intended to address exploits referred to as "Spectre" and "Meltdown." Implementation of these updates may make these results inapplicable to your device or system.

Configuration: Intel Core i5 processor 7600 at 3.50 GHz, 16 GB RAM, Intel Hyper-Threading Technology is not supported. Software: Intel C++ Compiler 18.0.1, GCC 7.2.0, Clang (LLVM front end) 5.0. Linux: Red Hat Enterprise Linux 7.2, kernel 3.10.0-514.4.5.el7.x86_64. Coremark Pro* Benchmark Compiler flags: Intel C++ Compiler 18.0.1: '-O3 -no-prec-div -ipo -xCORE-AVX2. GCC 7.2.0:'-Ofast -mfpmath=sse -flto -march=native -funroll-loops -ffat-lto-objects. Clang (LLVM front end) 5.0: -Ofast -mfpmath=sse -flto -march=native -funroll-loops. GCC and Clang 32-bit modes have an additional flag: –m32.

Benchmark source: Intel Corporation

1See below for further optimization notes and disclaimers.


benchmark for the Intel Atom processor

Benchmark results were obtained prior to implementation of recent software patches and firmware updates that are intended to address exploits referred to as "Spectre" and "Meltdown." Implementation of these updates may make these results inapplicable to your device or system.

Configuration: Intel Atom® processor C3958 at 2.00 GHz, 64 GB RAM, Intel Hyper-Threading Technology is not supported. Software: Intel C++ Compiler 18.0.1, GCC 7.2.0, Clang (LLVM front end) 5.0. Linux: Fedora* release 25, kernel 4.8.6-300.fc25.x86_64. Coremark Pro* Benchmark Compiler flags: Intel C++ Compiler 18.0.1: '-O3 -no-prec-div -ipo -xATOM_SSE4.2 -mtune=goldmont. GCC 7.2.0: '-Ofast -mfpmath=sse -flto -march=native -funroll-loops -ffat-lto-objects. Clang (LVM front end) 5.0: '-Ofast -mfpmath=sse -flto -march=native -funroll-loops. GCC and Clang 32-bit modes have an additional flag: –m32.

Benchmark source: Intel Corporation

1See below for further optimization notes and disclaimers.

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Software and workloads used in performance tests may have been optimized for performance only on Intel® microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations, and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information, visit Performance Benchmark Test Disclosure.

Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804