Intel® Xeon Phi™ Coprocessor Developer's Quick Start Guide

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Introduction

This document will help you get started writing code and running applications on a system (host) that includes the Intel® Xeon Phi™ Coprocessor based on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture). It describes the available tools and includes simple examples to show how to get C/C++ and Fortran-based programs up and running. For now, the developer will have to cut/paste the examples provided in the document to their system.

This document is available at http://software.intel.com/mic-developer under the "Overview"tab.

Goals

This document does:

  1. Walk you through the Intel® Manycore Platform Software Stack (Intel® MPSS) installation.
  2. Introduce the build environment for software enabled to run on Intel® Xeon Phi™ Coprocessor .
  3. Give an example of how to write code for Intel® Xeon Phi™ Coprocessor and build using Intel® Composer XE 2015.
  4. Demonstrate the use of Intel libraries like the Intel® Math Kernel Library (Intel® MKL).
  5. Point you to information on how to debug and profile programs running on an Intel® Xeon Phi™ Coprocessor .
  6. Share some best known methods (BKMs) developed by users at Intel.

This document does not:

  1. Cover each tool in detail. Please refer to the user guides for the individual tools.
  2. Provide in-depth training.

Summary of recent changes:

  • September 26, 2014: Intel(R) Xeon Phi(TM) Coprocessor Developer's Quick Start for Windows* (version 1.4) 
  • November 17, 2014: Intel(R) Xeon Phi(TM) Coprocessor Developer's Quick Start for Linux* (version 1.8)
For more complete information about compiler optimizations, see our Optimization Notice.

Comments

Jesmin,

Jesmin,

For questions like these, you should post them on the Intel Xeon Phi coprocessor forum (See the "ARTICLES / FORUMS / BLOGS" tab on http://software.intel.com/mic-developer.) Questions posted here are sometimes missed since they are monitored less frequently.

--
Taylor


Hi,

Hi,

I am getting an error like this:
HOST--ERROR:myoiOSSetPageAccess: mprotect failed!
Please increase the maximum of memory map areas
i.e. echo 256000 > /proc/sys/vm/max_map_count
How to fix this.

Also, is it possible for CPU and Coprocessor to simultaneously write on the same array?

Is it possible to reallocate a memory location which was previously allocated as _Cilk_shared *?

Thanks,
Jesmin




Hi Brice,

Hi Brice,

Intel(R) Xeon Phi(TM) coprocessors are numbered in the order in which they are discovered by PCI enumeration. The numbering is invariant as long as cards are not physically moved around. If cards are swapped between slots, the number associated with a physical card will change.
The pci_* entry in /sys/class/mic/mic* equates Phi(TM) card number *, with its PCI slot. It will look something like pci_02:00.00. The number is what you will see in lspci and references the slot number on the board.

Regards.


I am adding Xeon Phi locality

I am adding Xeon Phi locality information to hwloc (http://www.open-mpi.org/projects/hwloc/) so that people can find out which CPU cores and memory are close to which Phi board. I can use /sys/class/mic/mic%d to find the locality of a device. But do we know if device called "mic0" is the first device that is visible to the application through the different software interfaces? A competitor reorders its devices for some reason, does the Intel MIC driver reorder devices too?


I am sorry for not replying

I am sorry for not replying sooner. For some reasons, we did not get your questions.

Hi titanius.anglesmith: Intel(R) Xeon Phi(TM) supports standard linux programming including pthread. You just link with -pthread.

Hi drMikeT: For the first question, consider a coprocessor to be a separate node. There is no shared memory that is accessible between two different coprocessors, but shared memory communication is available within a single coprocessor.

PGAS support would be dependent on the implementation. If the PGAS environment is implemented using MPI and is compiled for MIC, it should work. For the most part, just treat it like another node with a different architecture.

Gergana has an article at http://software.intel.com/en-us/articles/how-to-run-intel-mpi-on-xeon-phi that gives a good overview.


Does the IntelMPI on MIC

Does the IntelMPI on MIC support shared-memory intra-node communication (i.e, among MIC cors) as it does with regular multi-core nodes?

Ar PGAs environmnets supported between MIC and th Host processor ? In the sensethat a process on the host and a process on MIC can "shar" memory ?

thanks

R/D High-Performance Computing and Engineering