Communication Optimizations in HPC Workshop

When: Nov 18, 2016
Where: Room 355-D, Salt Palace Convention Center. Salt Lake City, UT, United States
Type: Workshop

Bringing Researchers and Developers Together

This workshop brings together researchers and developers to foster discussion, collaboration, and ideas for optimizing communication and synchronization in high performance computing (HPC) applications.

As HPC applications scale to large super-computing systems, their communication and synchronization need to be optimized in order to deliver high performance. To achieve this, capabilities of modern network interconnect and parallel runtime systems need to be advanced and the existing ones to be leveraged optimally. Participants at this workshop will benefit from discussions, collaboration, and ideas that drive the design of future peta/exa-scale systems and HPC applications.

Keynote Address: Meeting the Communication Needs of Scalable Applications

Professor William D. Gropp, University of Illinois at Urbana-Champaign

The Message Passing Interface (MPI) is a successful API for developing libraries and applications. In practice, however, users and developers often find performance anomalies that can significantly impact scalability. This talk will discuss some of the applications' communication needs and how they differ from what is tested in basic communication benchmarks. Illustrations from several application codes and application benchmarks demonstrate that synchronizing data communication often limits performance, suggesting that maximizing communication bandwidth is insufficient for the applications' communication needs. These observations apply to other parallel programming models, and need to be addressed through programming model semantics and efficiently implementing programming systems that implement those models.

Call for Papers

This workshop brings together researchers and developers to present and discuss work on optimizing communication and synchronization in HPC applications. This includes:

  • State-of-the-art methodological and algorithmic advances in topology-aware or topology-oblivious blocking and non-blocking collective algorithms
  • Offloading of communication to network interface cards
  • Topology-aware process mappings for minimizing communication overhead on different network topologies such as dragonfly, high-dimensional torus networks, fat trees, optimizations for persistent communication patterns, studies, and solutions for inter-job network interference
  • Overlapping of communication with computation
  • Optimizing communication overhead in the presence of process imbalance
  • GPU-GPU and GPU-CPU communication

Specifically, we are looking for papers on these topics:

  • Blocking and non-blocking collective operations
  • Topology-aware collective algorithms and process mappings
  • Neighborhood collective optimizations
  • Communication offloading design and optimizations, such as offloaded triggered operations
  • Modeling and simulation of traffic patterns, including collectives, for generic or specific network topologies
  • Optimizations for persistent communication patterns
  • Inter-job network interference
  • Computation-communication overlap in HPC applications
  • Communication optimization in presence of process imbalance
  • Static or runtime tuning of collective operations
  • Scalable communication endpoints for manycore architectures
  • Communication optimizations on peta/exa-scale systems, heterogeneous systems, and GPUs
  • Network congestion studies and mitigation methods
  • Machine learning to optimize communication
  • Communication aspects of GPGPU, graph applications, or fault tolerance

Important Dates

Paper submission deadline September 11, 2016
Notification of acceptance September 28, 2016
Camera-ready copy October 11, 2016
Workshop dates November 18, 2016, 8:30 a.m. to 12:30 p.m.

Paper Submission Guidelines

  • Papers must follow the IEEE format (ACM format will be accepted for review but will have to be later changed to IEEE format during camera-ready submission).
  • We invite two kinds of submissions to this workshop:
    1. Full-length research papers (10-page limit)
    2. Short papers (5-page limit), which can take the form of position papers, experience reports, work in progress, late-breaking ideas, or surveys/comparisons. (The page limit does not include references, for which there is no page-limit.)
  • Papers should be submitted electronically via EasyChair.
  • Submitted papers should not have appeared in or be under consideration for a different workshop, conference, or journal.
  • Papers will be peer reviewed by the program committee for novelty, scientific merit, technical strength, originality, quality of presentation, and scope of the workshop. It is also expected that at least one author of an accepted paper must register for and attend the workshop.
  • Accepted papers will be published in the workshop proceedings by SIGHPC and made available in the ACM Digital Library and IEEE Xplore.
  • One outstanding paper selected by the program committee will be awarded the Best Paper Award (sponsored by Intel).

In cooperation with: