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Intel® Xeon Phi™ Coprocessor Technology Conference Presentations
Below are the presentations from the first Intel® Xeon Phi™ Coprocessor Technology Conference held in New York City, March 2013. The source code associated with these presentations is also available for download.
Intel® Xeon Phi™ Coprocessor Architecture Overview › (PPT)
Stepwise Optimization Framework › (PPT)
Leveraging Optimized Tools and Libraries › (PPT)
Scalar and Serial Optimization › (PPT)
Vectorization › (PPT)
Parallelization › (PPT)
Scale from Intel® Xeon® Processor to Intel® Xeon Phi™ Coprocessors › (PPT)
MPSS – The Software Stack › (PPT)
Source code for use with these presentations › (TAR)
Monte Carlo Demo
This demo shows how to benefit from Intel® Xeon® multi-core architecture using Intel tools. It shows incremental gains for the application with the help of Intel compilers, the Intel® Math Kernel Library (Intel® MKL), and OpenMP*. This has been achieved by minimal changes to the original CPU code.
The demo requires the installation of .NET framework, which is included in the bundle.
Hardware, Software, and BIOS Parameters
Financial Services Industry (FSI) - Frequently Asked Questions ›
Configuring and Tuning HP ProLiant* Servers for Low-Latency Applications" White Paper › (PDF)
Low Latency Settings for Dell* Machines › (PDF)
Red Hat* Low Latency Turning Guide › (PDF)
General Haswell Site ›
Haswell Instructions Set: including Intel® Advanced Vector extensions (Intel® AVX) Instructions ›
Intel® Transactional Synchronization Extensions (Intel® TSX) for Haswell has transaction lock instructions and ways to test them with Intel® Performance Counter Monitor (Intel® PCM) and Linux*:
Monitoring Intel Transactional Synchronization Extensions with Intel PCM ›
Intel Transactional Syncronization Extensions for Profiling with Linux* ›
Tools & Guides
Solaris to RHEL Strategic Migration Planning Guide ›
AIX to RHEL Strategic Migration Planning Guide ›
Profiling Tools ›
Performance Optimization ›
Optimizing the High Frequency Trading GatiRT* Application on the Latest Intel® Architecture Server ›
Intel® AVX: Instruction Set Architecture (ISA) Extensions ›